• Title/Summary/Keyword: Double-input

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Design of Robust High-Speed Motion Controller with Actuator Saturation and Its Application to Precision Positioning System (구동기 포화가 있는 견실 고속 온동 제어기 설계 및 정밀 위치 결정 시스템에의 적용)

  • Park, Hyun-Raek;Kim, Bong-Keun;Shh, Il-Hong;Chung, Wan-Kyun
    • Journal of Institute of Control, Robotics and Systems
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    • v.6 no.9
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    • pp.768-776
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    • 2000
  • A robust high-speed motion controller is proposed. The proposed controller consists of the proximate time optimal servomechai는 (PTOD) for high-speed motion, disturbance observer (DOB) for robustness, friction compensator, and saturation handling element, In the proposed controller, DOB basically provides the chance to apply PTOS to non-double integrator systems by drastically reducing disturbances as well as unwanted signals due to difference between real system and the double integrator model. But, in DOB-based systems, if control input is saturated due to control input PTOS and/or DOB, overall system stability cannot be guaranteed. To solve this problem, ribust stability, when the control input is saturated. Eventually, a simple saturation handling element is inserted to maintain internal stability of overall system. Also, we explain the our two saturation handling methods, Additional Saturation Element (ASE_ and Self Adjusting Saturation (SAS), are the equivalent solutions of the saturation problem to maintain internal stability. The stability and performance of the proposed controller are verified through numerical simulations and experiments using a precision linear motor system.

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A New Double-Talk Detection Algorithm (새로운 동시통화 검출 알고리즘)

  • Jung, Hong-Hee;Kim, Hyun-Tae;Park, Jang-Sik;Son, Kyung-Sik
    • Journal of Korea Multimedia Society
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    • v.11 no.3
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    • pp.281-291
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    • 2008
  • In this paper, we propose a new double talk detection algorithm which detects near end signals with less degradation, tracking echo path variation of echo canceler simultaneously. Our method makes use of a cross-correlation between channel input signals and estimated error signals and a normalized cross-correlation between microphone input signals and estimated error signals. By combing thresholds for these cross-correlations pertinently, this algorithm discriminates between variation of echo path and occurrence of double talk. These two cross-correlation are used to detect double talk periods, tracking echo path variation. During the detection period, adjustive adaptive filter is ceased to prevent the echo canceler from being disturbed by near end signals. Also, the echo canceler will still be kept on for tracking any variation in echo path. Through computer simulation results, it was confirmed that the proposed algorithm shows better performance, tracking echo path variation and detecting the double talk periods, than the Ye et. al's and the NLMS algorithms from ERLE viewpoint.

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Double Boost Power-Decoupling Topology Suitable for Low-Voltage Photovoltaic Residential Applications Using Sliding-Mode Impedance-Shaping Controller

  • Tawfik, Mohamed Atef;Ahmed, Ashraf;Park, Joung-Hu
    • Journal of Power Electronics
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    • v.19 no.4
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    • pp.881-893
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    • 2019
  • This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

  • Kwen, Hyeunwoo;Kim, Sang-Hwan;Lee, Jimin;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.29 no.2
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    • pp.82-88
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    • 2020
  • In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

Design of Double Digital Controller to Improve Performance for the Silent Discharging Ozonizer (무성방전 오조나이저의 성능개선을 위한 2중 디지털 제어기의 설계)

  • Park, Jee-Ho;Kim, Dong-Wan;Woo, Sung-Hoon;Roh, In-Bae;Woo, Jung-In
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.55 no.1
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    • pp.13-20
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    • 2006
  • In this paper, a control method of ozone generator for a tiny deodorizer is proposed, and also a cooling technique is described which is cooling down the flowing air gap into a silent discharger to $2[^{\circ}C]$ to generate ozone of high density and diffusing power. As the digital control system for this method, a double feedback loop is designed which detects the voltage and current of equivalent capacitor of the discharger and compensates for the poor power waveform caused by the noise at high discharging frequency. During the plant modeling of this system, computing time factor is considered as a unique parameter of the power system to improve the respond characteristics with regard to fluctuating load and to replenish the computing time delay of the controller. Through the experiment, sinusoidal input current for discharger can be acquired and all the effectiveness of this accurate control system over unstable ozone discharger are proved.

Numerical Analysis of Welding Residual Stress Using Heat Source Models for the Multi-Pass Weldment

  • Bae, Dong-Ho;Kim, Chul-Han;Cho, Seon-Young;Hong, Jung-Kyun;Tsai, Chon-Liang
    • Journal of Mechanical Science and Technology
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    • v.16 no.9
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    • pp.1054-1064
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    • 2002
  • Numerical prediction of welding-induced residual stresses using the finite element method has been a common practice in the development or refinement of welded product designs. Various researchers have studied several thermal models associated with the welding process. Among these thermal models, ramp heat input and double-ellipsoid moving source have been investigated. These heat-source models predict the temperature fields and history with or without accuracy. However, these models can predict the thermal characteristics of the welding process that influence the formation of the inherent plastic strains, which ultimately determines the final state of residual stresses in the weldment. The magnitude and distribution of residual stresses are compared. Although the two models predict similar magnitude of the longitudinal stress, the double-ellipsoid moving source model predicts wider tensile stress zones than the other one. And, both the ramp heating and moving source models predict the stress results in reasonable agreement with the experimental data.

Attitude Controller Design for a Bias Momentum Satellite with Double Gimbal (더블김벌을 장착한 바이어스 모멘텀 위성의 자세제어기 설계)

  • Park, Young-Woong;Bang, Hyo-Choong
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.32 no.4
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    • pp.34-42
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    • 2004
  • In this paper, a double gimbal is used for roll/yaw attitude control of spacecraft and two feedback controllers are designed. One is a PD controller of no phase difference between roll and yaw control input. The other is a PD controller with a phase lag compensator about the yaw control input. The phase lag compensator is designed a first order system and a lag parameter is designed for the control of yaw angle. There are two case simulations for each of controllers; constant disturbance torques and initial errors of nutation. We obtain the results through simulations that a steady-state error and a rising time of yaw angle are developed by the compensator. In this paper, simulation parameters use the values of KOREASAT 1.

X-Band 6-Bit Phase Shifter with Low RMS Phase and Amplitude Errors in 0.13-㎛ CMOS Technology

  • Han, Jang-Hoon;Kim, Jeong-Geun;Baek, Donghyun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.511-519
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    • 2016
  • This paper proposes a CMOS 6-bit phase shifter with low RMS phase and amplitude errors for an X-band phased array antenna. The phase shifter combines a switched-path topology for coarse phase states and a switch-filter topology for fine phase states. The coarse phase shifter is composed of phase shifting elements, single-pole double-throw (SPDT), and double-pole double-throw (DPDT) switches. The fine phase shifter uses a switched LC filter. The phase coverage is $354.35^{\circ}$ with an LSB of $5.625^{\circ}$. The RMS phase error is < $6^{\circ}$ and the RMS amplitude error is < 0.45 dB at 8-12 GHz. The measured insertion loss is < 15 dB, and the return losses for input and output are > 13 dB at 8-12 GHz. The input P1dB of the phase shifter achieves > 11 dBm at 8-12 GHz. The current consumption is zero with a 1.2-V supply voltage. The chip size is $1.46{\times}0.83mm^2$, including pads.

Operation Characteristic of Single-phase PFC converter with 1-switch Voltage Doubler Strategy (단일 스위치 배전압 방식의 단상 PFC 컨버터의 동작 특성)

  • Ku, Dae-Kwan;Ji, Jun-Keun;Cha, Guee-Soo;Lim, Seung-Beom;Hong, Soon-Chan
    • The Transactions of the Korean Institute of Power Electronics
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    • v.16 no.6
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    • pp.561-568
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    • 2011
  • This paper describes the operation characteristic of a single-phase PFC converter with 1-switch voltage doubler strategy for single-phase double-conversion UPS. A single-phase PFC converter with 1-switch voltage doubler strategy needs a diode bridge and one bidirectional active switch. Thus it is possible to reduce the material cost. However, the study results of operation characteristic and controller design has not been known after the converter circuit was proposed. For the performance evaluation of PFC converter, single-phase 3kVA double-conversion UPS was tested. The performance of PFC converter is experimentally confirmed with followings - input current reference traking, input power factor correction.

A Study on Solving of Double-layer Pattern Problem in Daejeon Correlator (대전상관기에서 복층패턴 문제의 해결에 관한 연구)

  • Oh, Se-Jin;Roh, Duk-Gyoo;Yeom, Jae-Hwan;Chung, Dong-Kyu;Oh, Chung-Sik;Hwang, Ju-Yeon
    • Journal of the Institute of Convergence Signal Processing
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    • v.16 no.4
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    • pp.162-167
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    • 2015
  • This paper describes the reason and the problem solving for the double-layer pattern of a Daejeon correlator operated in Korea-Japan Correlation Center. When the electric power of an input signal in the correlator is charged small enough to be buried in the noise, it is hard to see a signal with a specific pattern in the input signal, but when the electric power is large, a specific one is reported to be seen. By comparing data from observation with one from software correlator, it was confirmed from the analysis using the AIPS software that the amplitude gain of a source signal was affected about 3%. Therefore, in order to solve the problem of double-layer patterns, we found that a problem in the memory management module responsible for both the data input and the data serialization of the correlator is a cause for the double-layer pattern detected periodically. In other words, while data is serialized and read repeatedly in the memory area assigned to serialize the data from the serialization module, redundant last data is generated and an overlap for the memory allocation is occurred. Therefore, by modifying the program of the FPGA memory sections on serialization module to correct the problem, we confirmed that double-layer pattern is disappeared and correlation results are normally acquired.