• Title/Summary/Keyword: Discrete event system specification (DEVS)

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Algorithm for Transformation of Timed Petri Nets to DEVS Formalism (시간 페트리네트를 DEVS 형식론으로 변환하는 알고리즘)

  • 김영찬;김탁곤
    • Journal of the Korea Society for Simulation
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    • v.11 no.2
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    • pp.77-88
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    • 2002
  • Petri nets is a widely used formalism for specification and analysis of concurrent systems which is a subclass of discrete event systems. The DEVS (Discrete Event System Specification) formalism provides a general framework for specification of discrete event systems in a hierarchical, modular form. Often, modeling a discrete event system may employ both Petri Nets and DEVS formalism. In such a case low-level operational logics are modeled by Petri Nets and high-level managements by the DEVS formalism. Analysis of the system requires simulation of the overall system. This paper presents an algorithm for transformation of Petri Nets to DEVS formalism. The transformation enables modelers to simulate an overall system, which consists of DEVS models and Petri Nets models, in a unified DEVS simulation environment such as DEVSim++. An example for such transformation will be given.

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Logical Analysis of Real-time Discrete Event Control Systems Using Communicating DEVS Formalism (C-DEVS형식론을 이용한 실시간 이산사건 제어시스템의 논리 해석 기법)

  • Song, Hae Sang;Kim, Tag Gon
    • Journal of the Korea Society for Simulation
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    • v.21 no.4
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    • pp.35-46
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    • 2012
  • As complexity of real-time systems is being increased ad hoc approaches to analysis of such systems would have limitations in completeness and coverability for states space search. Formal means using a model-based approach would solve such limitations. This paper proposes a model-based formal method for logical analysis, such as safety and liveness, of real-time systems at a discrete event system level. A discrete event model for real-time systems to be analyzed is specified by DEVS(Discrete Event Systems Specification) formalism, which specifies a discrete event system in hierarchical, modular manner. Analysis of such DEVS models is performed by Communicating DEVS (C-DEVS) formalism of a timed global state transition specification and an associated analysis algorithm. The C-DEVS formalism and an associated analysis algorithm guarantees that all possible states for a given system are visited in an analysis phase. A case study of a safety analysis for a rail road crossing system illustrates the effectiveness of the proposed method of the model-based approach.

Object-Oriented Simulation of Container Terminal using a DEVS Formalism (DEVS 형식론을 이용한 컨테이너터미널의 객체지향 시뮬레이션에 관한 연구)

  • 성경빈;정희균;박용욱;이철영
    • Journal of Korean Port Research
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    • v.14 no.1
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    • pp.47-55
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    • 2000
  • In order to cope with the changes of container terminal situation in these days, many simulation studies for container terminal have been accomplished. But previous simulation studies using simulation language have limitations in model representation and difficulties in modeling of large scaled container terminal system. To make these problems better, this paper addresses an object-oriented simulation of container terminal system using a DEVS formalism. The DEVS(Discrete Event System Specification) formalism, developed by Zeigler, supports specification of discrete event system in a hierarchical and modular manner. The formalism provides a mathematical basis for studying discrete event systems with better understood and sounder semantics. In a step of system modeling, a DEVS formalism aims at the exact system modeling that has a basis of semantics and utilizing the object-oriented manner can flexibly cope with the changes of system environment. In this study a model is developed and verified through the simulation of some alternatives.

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Performance Evaluation of a Parallel DEVS Simulation Environment of P-DEVSIM ++ (병렬 DEVS 시뮬레이션 환경(P-DEVSIM ++) 성능 평가)

  • 성영락
    • Journal of the Korea Society for Simulation
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    • v.2 no.1
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    • pp.31-44
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    • 1993
  • Zeigler's DEVS(Discrete Event Systems Specification) formalism supports formal specification of discrete event systems in a hierarchical , modular manner. Associated are hierarchical, distributed simulation algorithms, called abstract simulators, which interpret dynamics of DEVS models. This paper deals with performance evaluation of P-DEVSIM ++, a parallel simulation environment which implements the DEVS formalism and associated simulation algorithms in a parallel environment. Performance simulator has been developed and used to experiment models of parallel simulation executions in different conditions. The experimental result shows that simulation time depends on both the number of processors in the parallel system and the communication overheads among such processors.

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A Model Formalization Methodology of Discrete Event Simulation with Formal Tools (형식 도구를 이용한 이산사건 시뮬레이션의 모델 형식화 방법론)

  • ;;Jeong, Young Sik;Baik, Doo Kwon
    • Journal of the Korean Operations Research and Management Science Society
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    • v.17 no.3
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    • pp.79-99
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    • 1992
  • The DEVS (Discrete Event system Specification) formal model for discrete event simulation is a hierarchical, modular model. Because the DEVS formal model has a mathematical structure, it provides a theoretic background of discrete event simulation model. However, the DEVS formal model is difficult to understand because of its mathematical structure. Also, since the DEVS formal model is often constructed by heuristic, subjective method of model designer from the model, a systematic model built-in methodology does not exist. In this paper, we propose the model formalization methodology from an informal model to the DEVS formal model. For this formalization methodology, we introduce formal tools for model construction based on the DEVS ( from an informal model : Event Dependency Graph (EDG) for the event analysis and State Representation Graph(SRG) for the system state analysis.

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Simulation Environment of DEVS Models using MATLAB/Simulink (MATLAB/Simulink를 이용한 DEVS 모델의 시뮬레이션 환경 구축)

  • Seo, Kyung-Min;Sung, Chang-Ho;Kim, Tag-Gon
    • Journal of the Korea Society for Simulation
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    • v.17 no.4
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    • pp.219-227
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    • 2008
  • The DEVS (Discrete Event Systems Specification) formalism supports specification of discrete event models in a hierarchical modular manner. MATLAB/Simulink is widely used for modeling, simulating and analyzing continuous and discrete time systems. This paper proposes a realization of the DEVS formalism in MATLAB/ Simulink. The proposed design enables to use a great amount of mathematical packages and functions included in MATLAB /Simulink. The design is also employed as real time simulation and hybrid system simulation which is a mixture of continuous systems and discrete event systems. The paper introduces Simulink-DEVS model, in which a simulation algorithm is embedded. The model consists of a Simulink-atomic model and a Simulink-coupled model. In addition, the time advance algorithm to simulate the model is suggested. The algorithm handles the time synchronization and the accommodation of different concepts specific to continuous and discrete event models. Two experimental results are presented for a pure discrete event model and a hybrid model.

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Implementation and Static Verification Methodology of Discrete Event Simulation Software based on the DEVS Diagram: A Practical Approach (DEVS 다이어그램 기반 이산사건 시뮬레이션 소프트웨어 구현 및 정적 검증기법: 실용적 접근방법)

  • Song, Hae Sang
    • Journal of the Korea Society for Simulation
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    • v.27 no.3
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    • pp.23-36
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    • 2018
  • Discrete Event System Specification (DEVS) has been used for decades as it provides sound semantics for hierarchical modular specification of discrete event systems. Instead of the mathematical specification, the DEVS diagram, based on the structured DEVS formalism, has provided more intuitive and convenient representation of complex DEVS models. This paper proposes a clean room process for implementation and verification of a DEVS diagram model specification into a simulation software source code. Specifically, it underlies a sequence of transformation steps from conformance and integrity checking of a given diagram model, translation into a corresponding tabular model, and finally conversion to a simulation source code, with each step being inversely verifiable for traceability. A simple example helps developers to understand the proposed process with associated transformation methods; a case study shows that the proposed process is effective for and adaptable to practical simulation software development.

Event-Driven Modeling and Simulation Method Applicable to Avionics System Integration Laboratory (항공용 SIL에 적용 가능한 이벤트 기반 모델링 및 시뮬레이션 방법)

  • Shin, Ju-chul;Seo, Min-gi;Cho, Yeon-je;Baek, Gyong-hoon;Kim, Seong-woo
    • Journal of Advanced Navigation Technology
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    • v.24 no.3
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    • pp.184-191
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    • 2020
  • Avionics System Integration Laboratory is the integrated test environment for integration and verification of avionics systems. When real equipment can not be used in the laboratory for various reasons, software models should be needed. Because there hasn't been any standardized method for the models so that it is difficult to reuse the developed models, the need for a framework to develop the avionics software models was emerged. We adopted DEVS(discrete event system specification) formalism as the standardized modeling method for the avionics software models. Due to DEVS formalism is based on event-driven algorithm, it doesn't accord a legacy system which has sequential and periodic algorithms. In this paper, we propose real-time event-driven modeling and simulation method for SIL to overcome these restrictions and to maximize reusability of avionics models through the analysis of the characteristics and the limitations of avionics models.

Modelling and Performance Evaluation of Packet Network by DEVS Simulation (DEVS 시뮬레이션을 이용한 패킷망의 모델링 및 성능분석)

  • 박상희
    • Journal of the Korea Society for Simulation
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    • v.3 no.1
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    • pp.75-88
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    • 1994
  • Discrete event modeling is finding ever more application to anlysis and design of complex manufacturing, communication, computer systems, etc. This paper shows how packet network systems may be advantageously represented as DEVS (Discrete Event System Specification) models by employing System Entity structure / Model base (SES/MB) framework developed by Zeigler. DEVS models and network structure representations support a strong basis for performance analysis of packet network systems. This approach is illustated in a typical packet network example with several routing strategies.

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GK-DEVS : Geometric and Kinematic DEVS for Simulation of 3 Dimensional Man-Made Systems (GK-DEVS : 3차원 인간제작 시스템의 시뮬레이션을 위한 형상 기구학 DEVS)

  • 황문호;천상욱;최병규
    • Journal of the Korea Society for Simulation
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    • v.9 no.1
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    • pp.39-54
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    • 2000
  • Presented in this paper is a modeling and simulation methodology for 3 dimensional man-made systems. Based on DEVS(discrete event system specification) formalism[13], we propose GK-DEVS (geometrical and kinematic DEVS) formalism to describe the geometrical and kinematic structure and continuous state dynamics. To represent geometry and kinematics, we add a hierarchical structure to the conventional atomic model. In addition, we employ the "empty event" and its external event function for continuous state changing. In terms of abstract simulation algorithm[13], the simulation method of GK-DEVS, named GK-Simulator, is proposed for combined discrete-continuous simulation. Using GK-DEVS, the simulation of an FMS(flexible manufacturing system) consisting of a luring machine, a 3-axis machine and a RGV-mounted robot has been peformed.en peformed.

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