• Structural Engineering and Mechanics
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• v.86 no.3
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• pp.291-309
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• 2023

This paper addresses the finite element modeling of functionally graded porous (FGP) beams for free vibration and buckling behaviour cases. The formulated finite element is based on simple and efficient higher order shear deformation theory. The key feature of this formulation is that it deals with Euler-Bernoulli beam theory with only three unknowns without requiring any shear correction factor. In fact, the presented two-noded beam element has three degrees of freedom per node, and the discrete model guarantees the interelement continuity by using both C⁰ and C¹ continuities for the displacement field and its first derivative shape functions, respectively. The weak form of the governing equations is obtained from the Hamilton principle of FGP beams to generate the elementary stiffness, geometric, and mass matrices. By deploying the isoparametric coordinate system, the derived elementary matrices are computed using the Gauss quadrature rule. To overcome the shear-locking phenomenon, the reduced integration technique is used for the shear strain energy. Furthermore, the effect of porosity distribution patterns on the free vibration and buckling behaviours of porous functionally graded beams in various parameters is investigated. The obtained results extend and improve those predicted previously by alternative existing theories, in which significant parameters such as material distribution, geometrical configuration, boundary conditions, and porosity distributions are considered and discussed in detailed numerical comparisons. Determining the impacts of these parameters on natural frequencies and critical buckling loads play an essential role in the manufacturing process of such materials and their related mechanical modeling in aerospace, nuclear, civil, and other structures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.43-53
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• 2003

Unlike in analog display devices, the physical screen resolution in digital devices are fixed from the manufacturing. It is a weak point on digital devices. The screen resolution displayed in digital display devices is varied. Thus, interpolation or decimation of the resolution on the display is needed to make the input pixels equal to the screen resolution., This process is called image scaling. Many researches have been developed to reduce the hardware cost and distortion of the image of image scaling algorithm. In this paper, we proposed a Winscale algorithm. which modifies the scale up/down in continuous domain to the scale up/down in discrete domain. Thus, the algorithm is suitable to digital display devices. Hardware implementation of the image scaler is performed using Verilog XL and chip is fabricated in a 0.5${\mu}{\textrm}{m}$ Samsung SOG technology. The hardware costs as well as the scalabilities are compared with the conventional image scaling algorithms that are used in other software. This Winscale algorithm is proved more scalable than other image-scaling algorithm, which has similar H/W cost. This image-scaling algorithm can be used in various digital display devices that need image scaling process.