• 터널과지하공간
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• 제15권4호
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• pp.275-287
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• 2005

지하공간 및 터널의 계획과 설계 단계에서 지반 조건과 관련한 정보는 경제성과 안정성 강화측면에서 매우 중요하다. 일반적으로 지반 조건은 RMR혹은 Q-system과 같은 공학적 암반 분류값을 이용하거나 지구물리 탐사의 결과 영상으로 표현할 수 있다. RMR이나 Q값은 설계를 위한 직접적 정보를 제공하나 그 대표 영역은 제한적이다. 반면 지구물리탐사 결과 영상은 전체 영역을 표현할 수 있는 반면 간접적인 정보만을 제공할 수 있다. 이와 같은 지반 정보들은 근본적으로 불확실성을 내포하고 있고, 서로 다른 공학적 단위로 표현되며 그 물리적 의미에서도 차이가 있다. 최근 크리깅이나 조건부 시뮬레이션과 같은 지구통계학적 방법들을 이용하여 전체 노선에 대한 RMR의 공간 분포를 추정해 왔었다. 본 연구에서는 주된 RMR 변량만을 이용하는 크리깅이나 조건부 시뮬레이션의 단점을 극복하기 위해 모의 담금질 기법을 적용하였다. 지구물리탐사 결과 영상을 참조영상으로 하여 RMR의 공간 분포를 추정하고 이와 결합된 불확실성을 평가하였다. 모의 담금질 기법은 주어진 제약조건을 만족시키도록 설계된 최적화 기법의 일종이다 RMR공간 분포 추정과 불확실성 평가를 위한모의 담금질 기법의 적용 과정을 제안하였다. 지반공학적 적용을 위해 RMR의 통계 모델과 지구물리탐사 결과 영상과의 상관성을 이용한 목적함수들을 정의하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.490.2-490.2
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• 2014

Since the general solar cells accept sun light at the front side, excluding the electrode area, electrons move from the emitter to the front electrode and start to collect at the grid edge. Thus the edge of gridline can be important for electrical properties of screen-printed silicon solar cells. In this study, the improvement of electrical properties in screen-printed crystalline silicon solar cells by contact treatment of grid edge was investigated. The samples with $60{\Omega}/{\square}$ and $70{\Omega}/{\square}$ emitter were prepared. After front side of samples was deposited by SiNx commercial Ag paste and Al paste were printed at front side and rear side respectively. Each sample was co-fired between $670^{\circ}C$ and $780^{\circ}C$ in the rapid thermal processing (RTP). After the firing process, the cells were dipped in 2.5% hydrofluoric acid (HF) at room temperature for various times under 60 seconds and then rinsed in deionized water. (This is called "contact treatment") After dipping in HF for a certain period, the samples from each firing condition were compared by measurement. Cell performances were measured by Suns-Voc, solar simulator, the transfer length method and a field emission scanning electron microscope. According to HF treatment, once the thin glass layer at the grid edge was etched, the current transport was changed from tunneling via Ag colloids in the glass layer to direct transport via Ag colloids between the Ag bulk and the emitter. Thus, the transfer length as well as the specific contact resistance decreased. For more details a model of the current path was proposed to explain the effect of HF treatment at the edge of the Ag grid. It is expected that HF treatment may help to improve the contact of high sheet-resistance emitter as well as the contact of a high specific contact resistance.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.