• Tunnel and Underground Space
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• v.15 no.4 s.57
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• pp.275-287
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• 2005

At the planning and design stages of a development of underground space or tunneling project, the information regarding ground conditions is very important to enhance economical efficiency and overall safety In general, the information can be expressed using RMR or Q-system and with the geophysical exploration image. RMR or Q-system can provide direct information of rock mass in a local scale for the design scheme. Oppositely, the image of geophysical exploration can provide an exthaustive but indirect information. These two types of the information have inherent uncertainties from various sources and are given in different scales and with their own physical meanings. Recently, RMR has been estimated in unsampled areas based on given data using geostatistical methods like Kriging and conditional simulation. In this study, simulated annealing(SA) is applied to overcome the shortcomings of Kriging methods or conditional simulations just using a primary variable. Using this technique, RMR and the image of geophysical exploration can be integrated to construct the spatial distribution of RM and to evaluate its uncertainty. The SA method was applied to solve an optimization problem with constraints. We have suggested the practical procedure of the SA technique for the uncertainty evaluation of RMR and also demonstrated this technique through an application, where it was used to identify the spatial distribution of RMR and quantify the uncertainty. For a geotechnical application, the objective functions of SA are defined using statistical models of RMR and the correlations between RMR and the reference image. The applicability and validity of this application are examined and then the result of uncertainty evaluation can be used to optimize the tunnel layout.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.490.2-490.2
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• 2014

Since the general solar cells accept sun light at the front side, excluding the electrode area, electrons move from the emitter to the front electrode and start to collect at the grid edge. Thus the edge of gridline can be important for electrical properties of screen-printed silicon solar cells. In this study, the improvement of electrical properties in screen-printed crystalline silicon solar cells by contact treatment of grid edge was investigated. The samples with $60{\Omega}/{\square}$ and $70{\Omega}/{\square}$ emitter were prepared. After front side of samples was deposited by SiNx commercial Ag paste and Al paste were printed at front side and rear side respectively. Each sample was co-fired between $670^{\circ}C$ and $780^{\circ}C$ in the rapid thermal processing (RTP). After the firing process, the cells were dipped in 2.5% hydrofluoric acid (HF) at room temperature for various times under 60 seconds and then rinsed in deionized water. (This is called "contact treatment") After dipping in HF for a certain period, the samples from each firing condition were compared by measurement. Cell performances were measured by Suns-Voc, solar simulator, the transfer length method and a field emission scanning electron microscope. According to HF treatment, once the thin glass layer at the grid edge was etched, the current transport was changed from tunneling via Ag colloids in the glass layer to direct transport via Ag colloids between the Ag bulk and the emitter. Thus, the transfer length as well as the specific contact resistance decreased. For more details a model of the current path was proposed to explain the effect of HF treatment at the edge of the Ag grid. It is expected that HF treatment may help to improve the contact of high sheet-resistance emitter as well as the contact of a high specific contact resistance.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.