• Title/Summary/Keyword: Direct 3-Phase Circuit Analysis

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A New fault Location Algorithm for a Line to Ground fault Using Direct 3-phase Circuit Analysis in Distribution Power Networks (3상회로 직접해석에 의한 배편계통 1선지락사고 고장거리 계산 알고리즘)

  • Choe, Myeon-Song;Lee, Seung-Jae;Lee, Deok-Su;Jin, Bo-Geon;Min, Byeong-Un
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.51 no.8
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    • pp.409-416
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    • 2002
  • This paper presents a fault location algorithm using direct 3-phase circuit analysis for distribution power networks. The unbalanced feature of distribution networks due to single phase loads or asymmetric operation prohibits us from using the conventional symmetrical component transformation. Even though the symmetrical component transformation provides us with a very easy tool in three phase network analysis, it is limited to balanced systems in utilizing its strong point, which is not suitable for distribution networks. In this paper, a fault location algorithm using direct 3-phase circuit analysis is developed. The algorithm is derived and it Is shown that the proposed method if we use matrix inverse lemma, is not more difficult then the conventional methods using symmetrical component transformation. Since the symmetrical component transformation is not used in the suggested method, unbalanced networks also can be handled with the same difficulty as balanced networks. The case study results show the correctness and effectiveness of the proposed algorithm.

Fault Location Algorithms for the Line to Ground Fault of Parallel-Circuit Line in Power Systems (전력계통 송배전선로 2회선 1선지락사고 고장거리 검출 알고리즘)

  • 최면송;이승재;강상희;이한웅
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.52 no.1
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    • pp.29-35
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    • 2003
  • This paper presents a fault location algorithm when there are parallel circuits in power system networks. In transmission networks, a fault location method using the distribution factor of fault currents is introduced and in distribution networks a method using direct 3-phase circuit analysis is developed, because the distribution networks are unbalanced. The effect of parallel circuits in fault location is studied in this paper. The effect is important for the range of protecting zones of distance relay in transmission networks and fault location in distribution networks. The result of developed fault location algorithm shows high accuracy in the simulation that using the EMTP.

New Fault Location Algorithms by Direct Analysis of Three-Phase Circuit Using Matrix Inverse Lemma for Unbalanced Distribution Power Systems

  • Park, Myeon-Song;Lee, Seung-Jae
    • KIEE International Transactions on Power Engineering
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    • v.3A no.2
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    • pp.79-84
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    • 2003
  • Unbalanced systems, such as distribution systems, have difficulties in fault locations due to single-phase laterals and loads. This paper proposes new fault locations developed by the direct three-phase circuit analysis algorithms using matrix inverse lemma for the line-to-ground fault case and the line-to-line fault case in unbalanced systems. The fault location for balanced systems has been studied using the current distribution factor, by a conventional symmetrical transformation, but that for unbalanced systems has not been investigated due to their high complexity. The proposed algorithms overcome the limit of the conventional algorithm using the conventional symmetrical transformation, which requires the balanced system and are applicable to any power system but are particularly useful for unbalanced distribution systems. Their effectiveness has been proven through many EMTP simulations.

A New Line to Line Fault Location Algorithm in Distribution Power Networks using 3 Phase Direct Analysis (3상회로의 직접해석에 의한 송배전계통 선간단락 사고 고장거리 계산 알고리즘)

  • Choe, Myeon-Song;Lee, Seung-Jae;Im, Seong-Il;Jin, Bo-Geon;Lee, Deok-Su
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.51 no.9
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    • pp.467-473
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    • 2002
  • In this paper, a fault location algorithm is suggested for line to line faults in distribution networks. Conventional fault location algorithms use the symmetrical component transformation, a very useful tool for transmission network analysis. However, its application is restricted to balanced network only. Distribution networks are, in general, operated in unbalanced manners, therefore, conventional methods cannot be applied directly, which is the reason why there are few research results on fault location in distribution networks. Especially, the line to line fault is considered as a more difficult subject. The proposed algorithm uses direct 3-phase circuit analysis, which means it can be applied not only to balanced networks but also to unbalanced networks like distribution a network. The comparisons of simulation results between one of conventional methods and the suggested method are presented to show its effectiveness and accuracy.

Design and fabrication of PSK carrier recovery circuit using multi-layer coupled line (다층형 결합 선로를 이용한 반송파 복원 회로 설계 제작)

  • Kim, Young-Wan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.10
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    • pp.2039-2044
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    • 2009
  • The PSK carrier signal recovery circuit using multi-layer coupled line was analyzed and designed. The fabricated carrier recovery 6 port element with multi-layer coupled line structure gets the simple architecture. It is possible to implement the carrier signal recovery circuit of the same structure with the multi-layer six port phase correlator of the direct receiver front-end. Based on the analysis of RML carrier recovery circuit using the multi-layer coupled line 6-port phase correlator, the multi-layer coupled line carrier signal recovery structure for multi-mode coherent demodulation was proposed. The fabricated multi-layer coupled line carrier signal recovery circuit for quadrature phase shift-keying shows a good carrier signal characteristic with a constant phase and phase error below ${\pm}3o$.

FPGA circuit implementation of despreading delay lack loop for GPS receiver and preformance analysis (GPS 수신기용 역확산 지연 동기 루프의 FPGA 회로 구현과 성능 분석)

  • 강성길;류흥균
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.3
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    • pp.506-514
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    • 1997
  • In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

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Hybrid Control Strategy of Phase-Shifted Full-Bridge LLC Converter Based on Digital Direct Phase-Shift Control

  • Guo, Bing;Zhang, Yiming;Zhang, Jialin;Gao, Junxia
    • Journal of Power Electronics
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    • v.18 no.3
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    • pp.802-816
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    • 2018
  • A digital direct phase-shift control (DDPSC) method based on the phase-shifted full-bridge LLC (PSFB-LLC) converter is presented. This work combines DDPSC with the conventional linear control to obtain a hybrid control strategy that has the advantages of linear control and DDPSC control. The strategy is easy to realize and has good dynamic responses. The PSFB-LLC circuit structure is simple and works in the fixed frequency mode, which is beneficial to magnetic component design; it can realize the ZVS of the switch and the ZCS of the rectifier diode in a wide load range. In this work, the PSFB-LLC converter resonator is analyzed in detail, and the concrete realization scheme of the hybrid control strategy is provided by analyzing the state-plane trajectory and the time-domain model. Finally, a 3 kW prototype is developed, and the feasibility and effectiveness of the DDPSC controller and the hybrid strategy are verified by experimental results.

A Design of K-Band Low Phase noise Oscillator by Direct Coupling of K-band Dielectric Resonator (유전체 공진기의 직접결합에 의한 K-Band 저위상잡음 발진기 설계)

  • Lim, Eun-Jae;Han, Geon-Hee;Rhee, Young-Chul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.1
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    • pp.17-24
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    • 2014
  • In this paper, we analysed coupling coefficient between dielectric resonator of high dielectric constant and microstrip line to design for low phase noise dielectric resonator by direct coupling. Also we analysed phase noise of dielectric resonance oscillator with parallel feedback circuit to complement Q by high dielectric constant. We obtained a result from high-stability dielectric oscillator which is optimum designed through analysis of dielectric resonance oscillator phase noise and coupling coefficient. The result is that the phase noise was -83.3dBc/Hz@1KHz at 20.25GHz when we used about 3.6 coupling coefficient and ${\epsilon}_r$=30 dielectric resonator of 20.25GHz dielectric resonance oscillator. As a result, we suggested the direct-connect design method by frequency multiplication mode to prevent phase noise loss at K-Band.

A new line to line fault location algorithm in distribution power networks using 3 phase direct analysis (3상회로의 직접해석에 의한 배전계통 선간단락 사고 고장거리 계산 알고리즘)

  • Jin, B.G.;Choi, M.S.;Lee, S.J.;Yoon, N.S.;Jung, B.T.;Lee, D.S.
    • Proceedings of the KIEE Conference
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    • 2002.07a
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    • pp.108-110
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    • 2002
  • In this paper, a fault location algorithm is suggested for line to line faults in distribution networks. Conventional fault location algorithms use the symmetrical component transformation, a very useful tool for transmission network analysis. However, its application is restricted to balanced network only. Distribution networks are, in general, operated in unbalanced manners, therefore, conventional methods cannot be applied directly, which is the reason why there are few research results on fault location in distribution networks. Especially, the line to line fault is considered as a more difficult subject. The proposed algorithm uses direct 3-phase circuit analysis, which means it can be applied not only to balanced networks but also to unbalanced networks like distribution a network. The comparisons of simulation results between one of conventional methods and the suggested method are presented to show its effectiveness and accuracy.

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Operating properties of superconducting fault current limiters with a sing1e line-to-ground fault in a three-phase system (3상 전력계통의 1선 지락사고에 대한 초전도한류기의 동작특성)

  • 최효상;현옥배;김혜림;황시돌;차상도
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2003.02a
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    • pp.261-262
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    • 2003
  • We performed unsymmetrical analysis of a single line-to-ground fault in a three-phase system. The current limiting elements were meander type YBCO stripes coated with Au shunt. When the fault occurred, short circuit currents were effectively limited within 1-2 msec after fault instant. The unsymmetrical rate of fault phase was distributed from 6.4 to 1.4 and most of the fault current flowed in the grounding line due to its direct grounding system.

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