• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.950-953
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• 1987

A wave difference method(WDH) phase detector for timing recovery is designed in the digital subscriber loop receiver. This paper describes the architecture and experimental results of the WDM, tankless timing extraction PLL. The results show that the designed WDM timing extraction circuit have stable jitter performance without the use of high precision LC tank circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.829-835
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• 2002

DSL(digital subscriber line) transceiver designers have concerned the impulsive noise as well as NEXT(near-end crosstalk) and FEXT(far-end crosstalk) immunities Down as the strongest sources that limit the DSL channel capacity. In these noise environment the analysis on the performance of DSL should be needed. Therefore, in this paper we have estimated and simulated the SNR(signal-to-noise ratio) margin of DMT(discrete multi-tone) signal in Gauss, NEXT, FEXT and impulse noise environment by modeling an Middleton's Class A impulse signal with the test Cook pulses. As a result, it is known that the transmission rate of uplink is limited by noise characteristics rather than by loop length, but that of downlink limited complexly by both of noise characteristics and loop length. In conclusion, these results will be utilized as the threshold of ADSL performance in the complex noise environment including impulse noise.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.05c
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• pp.410-415
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• 2002

최근 초고속인터넷과 다채널 방송, VOD(Video on Demand), HDTV 등의 광대역 통합 서비스와 음성, 음악, 원격강시, 화상전화/회의 등의 부가기능을 제공하는 통신 서비스를 동시에 수용하기 위해 VDSL(Very high speed Digital Subscriber Loop)에 대한 연구가 진행중이다. 본 논문에서는 DSL 포럼 및 FS-VDSL 위원회의 기고서와 규격를 바탕으로 ATM과 IP 기반의 VDSL물 이용한 디지털 방송 서비스를 제공하기 위한 종단간 ATM 모델과 ATM-IP 연동 모델에 대한 망의 구성 및 프로토콜 스택을 제시하고 비교 분석한다. 그리고 ATM/VDSL 기반에서 DSM-CC(Digital Storage Media Command and Control)와 IGMP(Internet Group Management Protocol) 프로토콜을 이용한 디지털 방송 서비스 제공 절차를 제안한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.687-694
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• 1999

In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.3
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• pp.119-125
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• 2014

Echo cancellation is required for a dual-duplex high speed communication such as digital subscriber line(DSL), in order to allow each individual loop to operate in a full duplex fashion. Echo cancellation was one of the most difficult aspects of DSL design, requiring high linearity and total echo return loss in excess of 70 dB. For a long and rapidly changing echo response, if the echo is cancelled by an adaptive echo canceller, the echo canceller needs more taps and its performance is decreased. But if the response is divided into several responses, which response is estimated by a adaptive digital filter and combined, the computation complexities are decreased and the performance is increased. Therefore, the adaptive multi-stage echo canceller is proposed to decrease the computation complexity and increase the performance of echo return loss, in which the echo canceller is composed of several stage echo canceller estimating each divided echo response. Through computer simulations, this multi-stage echo canceller is verified to have merits for high speed communications such as DSL application.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.113-120
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• 2014

In this paper, I present a new echo canceller using the adaptive cascade system identification (CSI) method, which a system response is divided into several responses so that each response is adaptively estimated and combined. Echo cancellation is required for a dual-duplex DSL, in order to allow each individual loop to operate in a full duplex fashion. Echo cancellation was one of the most difficult aspects of DSL design, requiring high linearity and total echo return loss in excess of 70 dB. Especially, for a fickle response, if the response is estimated by an adaptive filter, the filter needs more taps and the performance is decreased. But the response is divided into several responses, the computation complexities are decreased and the performance is increased. For the stage constant n, which represents the number of stages, if the response is not divided (n=1), the computation complexity of multiply is $2N^2$. And if the response is divided into two responses (n=2), the computation complexity of multiply is $2N^2$. Also, if n=3, the computation complexity is ${\frac{2}{3}}N^2$. Therefore, it is known that the computation complexity is decreased as n is increased. Finally, this proposed method is verified through simulation of echo canceller for digital subscriber line (DSL) application.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.11
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• pp.37-43
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• 1998

This paper proposes a new echo canceller that can be used in a full-duplex digital subscriber loop modem. The proposed echo canceller uses a NLMS-based parallel adaptation NLMS (PA-NLMS) algorithm. The PA-NLMS algorithm that an estimate of the nonstationarity to additive noise ratio (NNR) gained from two distinct NLMS processes is used to select the value of NLMS convergence-controlling parameter has been developed. Numerical results based on computer simulation show that the proposed algorithm has a convergence rate approaching that of the fastest possible NLMS process while improving on its MAC performance considerably.