• Title/Summary/Keyword: Digital instrumentation and control

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Development of a Digital System for Protection and Control of a Substation Part 1 - Development of hardware (변전소의 보호.제어를 위한 디지탈 시스템 개발 PART 1 - 하드웨어 개발)

  • Kwon, W.H.;Lee, Y.I.;Park, H.K.;Park, S.H.;Kim, M.J.;Moon, Y.S.;Yoon, M.C.;Kim, I.D.;Lee, J.H.
    • Proceedings of the KIEE Conference
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    • 1992.07a
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    • pp.359-361
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    • 1992
  • This paper describes the development of an Integrated Digital Protection And Control System (IDPACS) for 345 KV substation. The developed IDPACS system containes digital protection units for transmission lines, delivery lines, transformers, bus, shunt reactors and Shunt capacitors. We deloped a Local Area Network (LAN) Which connects the digital protection units to the station computer for monitoring and control purposes.

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DSP-Based Digital Controller for Multi-Phase Synchronous Buck Converters

  • Kim, Jung-Hoon;Lim, Jeong-Gyu;Chung, Se-Kyo;Song, Yu-Jin
    • Journal of Power Electronics
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    • v.9 no.3
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    • pp.410-417
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    • 2009
  • This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

Introduction of Requirements and Regulatory Guide on Cyber Security of I&C Systems in Nuclear Facilities (원전 계측제어시스템의 사이버보안 요구사항)

  • Kang, Young-Doo;Jeong, Choong-Heui;Chong, Kil-To
    • Proceedings of the KIEE Conference
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    • 2008.10b
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    • pp.209-210
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    • 2008
  • In the case of unauthorized individuals, systems and entities or process threatening the instrumentation and control systems of nuclear facilities using the intrinsic vulnerabilities of digital based technologies, those systems may lose their own required functions. The loss of required functions of the critical systems of nuclear facilities may seriously affect the safety of nuclear facilities. Consequently, digital instrumentation and control systems, which perform functions important to safety, should be designed and operated to respond to cyber threats capitalizing on the vulnerabilities of digital based technologies. To make it possible, the developers and licensees of nuclear facilities should perform appropriate cyber security program throughout the whole life cycle of digital instrumentation and control systems. Under the goal of securing the safety of nuclear facilities, this paper presents the KINS' regulatory position on cyber security program to remove the cyber threats that exploit the vulnerabilities of digital instrumentation and control systems and to mitigate the effect of such threats. Presented regulatory position includes establishing the cyber security policy and plan, analyzing and classifying the cyber threats and cyber security assessment of digital instrumentation and control systems.

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Fuzzy Logic PID controller based on FPGA

  • Tipsuwanporn, V.;Runghimmawan, T.;Krongratana, V.;Suesut, T.;Jitnaknan, P.
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1066-1070
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    • 2003
  • Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

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Digital Control of Phase-Shifted Full-Bridge PWM Converter

  • Lim, Jeong-Gyu;Chung, Se-Kyo
    • Journal of Power Electronics
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    • v.8 no.3
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    • pp.201-209
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    • 2008
  • This paper presents the modeling and design of a digital controller for a phase-shifted full-bridge converter (PSFBC) in a discrete-time domain. The discretized PSFBC model is first derived and then analyzed considering the sampling effect and the system parameters. Based on this model, the digital controller is directly designed in a discrete-time domain. The simulation and experimental results are provided to show the validity of the proposed modeling and controller design.

Digital Hearing Aids Specific $\mu$DSP Chip Design by Verilog HDL

  • Jarng, Soon-Suck;Chen, Lingfen;Kwon, You-Jung
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.190-195
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    • 2005
  • The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

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Digital IF Designs for SDR in Simulink (Simulink에서의 SDR을 위한 Digital IF 설계)

  • Woo, Choon-Sic;Kim, Jae-Yoon;Lee, Chang-Soo;Yoo, Kyung-Yul
    • Proceedings of the KIEE Conference
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    • 2002.07d
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    • pp.2589-2591
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    • 2002
  • 송수신기의 방식에는 직접변환 방식과 기저대역 신호와 LO(Local Oscillator)를 혼합하여 interpolation 기법을 사용하여 중간 주파수 단계까지 up conversion을 하고 두 번째 LO와 IF신호를 혼합하여 RF신호로 변환하여 송신하는 헤테로다인 방식이 존재한다. 본 논문에서는 이런 송수신기 방식 중에서 헤테로다인 방식을 적용하여 QPSK에서의 digital up /down converter를 Simulink 환경에서 설계 및 구현하였다. Up converter는 4배의 interpolation 필터와 4단짜리 cascaded integrate-comb(CIC)필터를 사용하여 입력데이터의 샘플 레이트를 클럭 레이트까지 증가시켰으며, numerically controlled oscillator (NCO)와 mixer를 사용하여 신호를 변조하였다. Down converter의 구조는 up converter와 동일하며 단지 up converter의 반대순서로 구성되어있다. 이런 모든 과정을 Simulink를 이용한 시뮬레이션과 스펙트럼 분석기를 사용하여 검증해 보았다.

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Digital Hearing Aid DSP Chip Parameter Fitting Optimization

  • Jarng, Soon-Suck;Kwon, You-Jung;Lee, Je-Hyung
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1820-1825
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    • 2005
  • DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed features from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

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A Study of Improvement on the responsiveness of Digital AVR System (Digital 자동전압조정장치(AVR)의 속응성 향상에 관한 연구)

  • Kim, Song-hyun;Lee, Hyung-ki;Choe, Wook-yeon;An, Young-joo;Kim, Hyun-soo;Kim, Gi-Ryang
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.246-247
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    • 2015
  • Type of Automatic Voltage Regulator (AVR) can be divided into Analog and Digital Type. Automatic Voltage Regulator (AVR) of the synchronous generators of the brushless type are to be reduced to the voltage fluctuation on the basis of the total load. The PID control method is a general control technique is commonly widely used. In this study, the control target parameter iPID does not reset the parameters of the controller for the variable (Intelligent PID) using the controller synchronous generator Digital automatic voltage to you like all applied to the adjusting device (AVR) the voltage change is small, improved responsiveness was studied in this controller.

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Development of a Digital System for Protection and Control of a Substation Part 2 - Development of Fiber Optic Network (변전소의 보호.제어를 위한 디지탈 시스템 개발 PART 2 - 광 통신망 개발)

  • Kwon, W.H.;Park, S.H.;Kim, M.J.;Lee, Y.I.;Park, H.K.;Moon, Y.S.;Yoon, M.C.;Kim, I.D.;Lee, J.H.
    • Proceedings of the KIEE Conference
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    • 1992.07a
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    • pp.362-364
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    • 1992
  • In this paper, the development of a fiber optic network for an integrated digital protection relay system is described. The structure of the developed network is determined to loosen the optic requirements and to have good extensibility while providing sufficient functions for protection and control for substations. The network has a hierarchical structure with two levels. The upper level handles data for monitoring and control of the system with star topology. The lower level manages the real time data for bus protection with one-to-one connections. Communication flows of each level are described. The HDLC is employed as the network protocol.

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