• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.261-269
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• 2005

Throughout the history of digital communication, the digital speech coder is used as speech compression tool. Nowadays, the speech coder has been rapidly developed in the area of mobile communication system to overcome severe channel error and limitation of radio frequency resources. Due to the development of high performance communication system, high quality of speech coder is needed. This kind of speech coder can be used not only in communication services but also in digital multimedia services. In this paper, we describe the technologies of digital speech coder which are used in wire and wireless communication. We also present a summary of recent speech coding standards for narrowband and wideband applications. Finally we introduce the technical trends of next generation speech coder.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of Korean Society of Archives and Records Management
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• v.24 no.1
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• pp.163-186
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• 2024

With the National Archives of Korea's establishment of the Selection Criteria for Preservation Format of Digital Records (v1.0) in 2022, criteria have been formed to facilitate the selection of appropriate preservation formats for various types of digital records. With the advancement of technology, diverse electronic file types are produced. However, no specific criteria exist for records other than document types, such as PDF/A-1b. Therefore, the purpose of this paper is to derive intrinsic criteria for selecting preservation formats for audiovisual records, particularly focusing on video-type digital records, to expand the scope of the preservation format selection criteria. Initially, significant properties of video-type digital records were determined, forming the basis for the intrinsic criteria. According to these properties, the video types were categorized into container type and codec type, and three and six evaluation criteria items were derived, respectively. By structuring evaluation criteria for each attribute, this paper proposes intrinsic criteria for selecting preservation formats for video-type electronic records.

• Journal of Broadcast Engineering
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• v.21 no.3
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• pp.357-368
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• 2016

In DAB+, HE-AAC v2 codec is applied for the fixed rate transmission of audio stream. In case that xHE-AAC codec including USAC, a more efficiency is expected when the variable frame is used in a given same bandwidth compared to the fixed frame transmission. For this to be realized, audio streams need to be multiplexed in a sub-channel before transmission, then a method is required to identify the border of each audio frames. In this paper, the toggled sync byte and additional identification field being sequentially placed between AU borders are proposed in order to deal with the AU border identification. In addition, the Reed-Solomon based error correction code which is compliant to DAB+ is proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.962-970
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• 2004

This paper presents an efficient implementation of the 2.4 kbps EHSX(Enhanced Harmonic Stochastic Excitation) speech coder on a TMS320C6701$^{TM}$ floating-point digital signal processor. The EHSX speech codec is based on a harmonic and CELP(Code Excited Linear Prediction) modeling of the excitation signal respectively according to the frame characteristic such as a voiced speech and an unvoiced speech. In this paper, we represent the optimization methods to reduce the complexity for real-time implementation. The complexity in the filtering of a CELP algorithm that is the main part for the EHSX algorithm complexity can be reduced by converting program using floating-point variable to program using fixed-point variable. We also present the efficient optimization methods including the code allocation considering a DSP architecture and the low complexity algorithm of harmonic/pitch search in encoder part. Finally, we obtained the subjective quality of MOS 3.28 from speech quality test using the PESQ(perceptual evaluation of speech quality), ITU-T Recommendation P.862 and could get a goal of realtime operation of the EHSX codec.c.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.563-568
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• 2007

We propose the computation reduction method of real root method that is used in the EVRC(Enhanced Variable Rate Codec) system. The real root method is that if polynomial equations have the real roots, we are able to find those and transform them into LSP. However, this method takes much time to compute, because the root searching is processed sequentially in frequency region. But, the important characteristic of LSP is that most of coefficients are occurred in specific frequency region. So, to reduce the computation time of real root, we used the met scale that is linear below 1kHz and logarithmic above. In order to compare real root method with proposed method, we measured the following two. First, we compared the position of transformed LSP(Line Spectrum Pairs) parameters in the proposed method with these of real root method. Second, we measured how long computation time is reduced. The experimental result is that the searching time was reduced by about 48% in average without the change of LSP parameters.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.1
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• pp.57-65
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• 2012

People leave voicemails or record phone conversations in their daily cell phone use. Sometimes important voice data is deleted by the user accidently, or purposely to cover up criminal activity. In these cases, deleted voice data must be able to be recovered for forensics, since the voice data can be used as evidence in a criminal case. Because cell phones store data that is easily fragmented in flash memory, voice data recovery is very difficult. However, if there are identifiable patterns for the deleted voice data, we can recover a significant amount of it by researching images of it. There are several types of voice data, such as QCP, AMR, MP4, etc.. This study researches the data recovery solutions for EVRC codec and AMR codec in QCP file, Qualcumm's voice data format in cell phone.

• The Journal of the Acoustical Society of Korea
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• v.21 no.3
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• pp.237-244
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• 2002

In this paper we mention the optimization of MPEG-4 VM (Moving Picture Expert Group-4 Verification Model) GA (General Audio) AAC (Advanced Audio Coding) encoder and the design of the decoder for PDA (Personal Digital Assistant) using MPEG-4 VM source. We profiled the VMC source and several optimization methods have applied to those selected functions from the profiling. Intel Pentium III 600 MHz PC, which uses windows 98 as OS, takes about 20 times of encoding time compared to input sample running time, with additional options, and about 10 times without any option. Decoding time on PDA was over 35 seconds for the 17 seconds input sample. After optimization, the encoding time has reduced to 50% and the real time decoding has achieved on PDA.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.3
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• pp.1-14
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• 2019

The 4th Industrial Revolution, intelligent automobile application technology is evolving beyond the limit of the mobile device to a variety of application software and multi-media collective technology with big data-based AI(artificial intelligence) technology. with the recent commercialization of 5G mobile communication service, artificial intelligent automobile technology, which is a fusion of automobile and IT technology, is evolving into more intelligent automobile service technology, and each multimedia platform service and application developed in such distributed environment is being developed Accordingly, application software technology developed with a single system SoC of a portable terminal device through various service technologies is absolutely required. In this paper, smart device design for ontology design of intelligent automobile open platform enables to design intelligent automobile middleware software design technology such as Android based SVC Codec and real time video and graphics processing that is not expressed in single ASIC application software technology as SoC based application designWe have experimented in smart device environment through researches, and newly designed service functions of various terminal devices provided as open platforms and application solutions in SoC environment and applied standardized interface analysis technique and proved this experiment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.