• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.647-654
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• 2005

In this paper, we implemented a terrestrial/cable PSIP converting system, so-called a PSIP converter, which is converting a terrestrial PSIP into a cable PSIP for a data broadcasting service in the interoperable network of terrestrial and cable, and define an interface between the PSIP converter and the OOB SI generator by using PMCP messages compliant to ATSC T3/Sl. The exiting PSIP converter just converts a terrestrial PSIP into a cable PSIP compliant to ATSC and OCAP standard and transmits by a MPEG-2 TS format. That is to say, it is not for the digital data broadcasting but for the digital broadcasting. In addition, the PSIP converter can support various types of PSIP information to the OOB SI generator by using PMCP messages defined by a hierarchical structure as per each channel, audio/video event, data event and so on.

• Journal of Satellite, Information and Communications
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• v.4 no.2
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• pp.34-38
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• 2009

This paper is related with optimum burst structure design for high efficient TDMA satellite return link transmission. In general, some typical burst structure for data transmission is composed of a pair of preamble and traffic data in the DVB-RCS (Digital Video Broadcasting. Return Channel via Satellite) and IPOS (IP over Satellite) standard. This structure has some difficulties to increase spectral efficiency that it requires a large of preamble length, high SNR environment, or receiver complexity. To cope with them, burst structure with distributed pilot symbol can be used to alleviate the residual frequency offset effect by calculating accurate frequency offset than conventional one. In particular, we investigate some relevant to proposed distributed pilot structure, previously and analyze their strong points/drawbacks in terms of synchronization to draw the most appropriate one.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.243-245
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• 2014

본 논문에서는 OFDM(Orthogonal Frequency Division Multiplexing)시스템에서 OFDM 심벌 타이밍 옵셋에 따른 4096QAM 의 uncoded-BER(Bit Error Rate) 및 성상도를 측정하였다. uncoded-BER 은 수신기의 FEC(Forward Error Correction) 복호기 이전에서 측정된 BER 을 의미한다. 측정을 위해, OFDM 을 사용하는 DVB-C2(Digital Video Broadcasting for Cable Systems 2) 송수신기를 FPGA(Field Programmable Gate Array)를 이용하여 구현하였으며, OFDM 심벌의 CP(Cyclic Prefix)를 이용하여 OFDM 심벌 동기를 수행하였다. 일반적으로, OFDM 심벌 동기는 OFDM 심벌에서 CP 가 반복된다는 특성을 이용한 상관기를 사용한다. 또한, ISI(Inter Symbol Interference) 및 ICI(Inter Channel Interference)를 최소화하기 위해, 채널의 최대 지연시간을 고려하여 CP 내에서 OFDM 심벌 동기가 획득된다. 이럴 경우 수신기에서는 각 부반송파에 할당된 QAM 심벌들의 위상 회전이 발생하지만, 등화기에서 이러한 위상 회전이 보상된다. 부반송파에 할당된 파일롯 심벌들을 이용하여 채널 추정 및 보상을 하는 등화기에서, 파일롯 심볼들도 OFDM 심벌 타이밍 옵셋에 의해 위상회전이 발생하기 때문에 채널 추정 값에 영향을 미친다. 따라서, 본 논문에서는 4096QAM 과 ZF-LE(Zero Forcing Linear Equalizer)를 사용한 경우, OFDM 심벌 타이밍 옵셋에 따른 uncoded-BER 및 성상도의 측정 결과를 제시하였다.

• ETRI Journal
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• v.41 no.3
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• pp.308-315
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• 2019

Due to its high spectrum efficiency, 64-amplitude phase-shift keying (64-APSK) is one of the primary technologies used in deep space communications and digital video broadcasting through satellite-second generation. However, 64-APSK suffers from considerable computational complexity because of the de-mapping method that it employs. In this study, a low-complexity de-mapping method for (4 + 12 + 20 + 28) 64-APSK is proposed in which we take full advantage of the symmetric characteristics of each symbol mapping. Moreover, we map the detected symbol to the first quadrant and then divide the region in this first quadrant into several partitions to simplify the formula. Theoretical analysis shows that the proposed method requires no operation of exponents and logarithms and involves only multiplication, addition, subtraction, and judgment. Simulation results validate that the time consumption is dramatically decreased with limited degradation of bit error rate performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.2
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• pp.1-7
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• 2020

In modern society, as technology has advanced and human life area has expanded, there has been an increasing demand for high-quality voice and video communications services without restrictions on time and place. In response to this demand, satellite communications systems that provide a wide range of communications and that offer multiple access are evolving day by day. In satellite communications systems such as Digital Video Broadcasting - Return Channel Via Satellite (DVB-RCS) and Warfighter Information Network-Tactical (WIN-T), the multi-frequency time division multiple access (MF-TDMA) demand assigned multiple access (DAMA) scheme is used for efficient resource allocation. In this scheme, since the satellite terminals periodically request resources from the network controller, and the network controller dynamically allocates resources, it is necessary to arrange resource allocation information from time to time. Shortening of the alignment time is a more important factor in a satellite communications system in which a long transmission delay occurs due to long-distance transmission and reception. In this paper, we propose a sorting algorithm variable-selection scheme that shortens the sorting time by cross-selecting the sorting algorithm based on a threshold value, while setting the number of frames in the MF-TDMA DAMA satellite communications system as the threshold value.