• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.109-117
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• 2015

In this paper, we proposed error-reducing method to source or measure a current or voltage for LED in the I-V characteristic analysis system using a digital signal processor (DSP). this method has the advantage of reducing a non-linear circuit error and random error. random error can be reduced using recursive averaging technique and non-linear circuit error can be reduced using 2rd polynomial regression calibration parameters fitting with measured sample data. it corrects measured error of IR, VR, VF1, VF2, VF3 of LED using calibration parameters. experimental results show that can be performed with about 0.017~0.043% accuracy.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1178-1183
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• 1990

A digital signal processor(DSP) is applied to realizing a compensator of control system of active magnetic bearings, to restrict a resonance caused by the first-order bending vibration of a flexible rotor, and to run the rotor beyond the critical speed. A full-order observer is applied to the translatory rotor-motion with the first-order vibration mode. A PID control is used for the conical motion. The rotor used in the experiments is symmetric, and an electromagnet and a displacement sensor are set in collocation.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.138-147
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• 2005

This paper presents a SPMSM(Surface-mounted Permanent Magnet Synchronous Motor) servo drive system using high performance TMS320F2812 DSP for the industrial application. The DSP(Digital Signal Processor) Controller enables an enhanced real time algorithm and cost-effective design intelligent for only exclusively motor drives which can be yield enhanced operation, fewer system components, lower control system cost, increased efficiency and high performance. The suggested system contain speed and current sensing circuits, SVPWM(Space Vector Pulse Width Modulation) and I/O interface circuit. The developed servo drive control system showns a good response characteristics results and high performance features in general purposed 400[w] machine. This system can achieve cost reduction and size minimization of controllers.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• KIPE Magazine
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• v.9 no.2
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• pp.23-25
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• 2004

1980년대 초반까지 대부분의 제어기는 아날로그 형태로 구성되어 복잡한 연산을 수행하기에는 많은 제약이 있었으나, 1980년대 초반부터 일반에게 소개되기 시작한 마이크로프로세서는 과거 불가능하다고 여겨졌던 연산을 현실화하는 계기를 마련하였다. 초기에는 8비트 혹은 16비트 형태의 마이크로프로세서가 주류를 이루었으나. 컴퓨터 및 반도체 분야의 눈부신 발달에 힘입어 80년대 중반에는 32비트 고성능 Digital Signal Processor(DSP)가 출현하게 된다.(중략)

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.93-99
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• 2018

This paper presents an implementation method using NDK (Network Developer's Kit) of GNU (GNU is Not Unix) Radio and Multicore DSP (Digital Signal Processor) to implement LTE (Long Term Evolution) SDR (Software Defined Radio) Platform. In order to satisfy 1.4MHz, 3MHz, 5MHz and 10MHz of the bandwidth supported by LTE, USRP (Universal Software Radio Peripheral) X series which is an RF (Radio Frequency) transceiver of Ettus Research was used. To control this, GNU Radio which is an open source software radio toolkit was used. We also used NDK from TI (Texas Instruments) DSP to transfer data between USRP and DSP. Experimental results show throughput results according to each bandwidth, thus confirming the feasibility of implementing LTE SDR Platform using GNU Radio and NDK of TI DSP.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.3
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• pp.275-281
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• 2014

Recently, the need for various underwater application systems targeting efficient resource exploration and aquatic ecosystem monitoring is rapidly increasing in littoral sea and inland waters. In this paper, we focus on the research and development of digital module of acoustic micro modem which can be used for underwater mobile communication systems and underwater sensor network systems. Specifically, a digital module of acoustic modem embedding digital signal processor is designed and implemented. On top of the developed hardware platform, physical layer frame generation and recovery and channel coding algorithms are mounted and tested in a water tank and a pond to verify its functionality and performance. According to experimental results, less than 1 percent of total computational power is consumed in the processing of frame control and convolutional code with the data rate of 1 kbps. Thus, the performance of micro modem could be improved by loading efficient baseband algorithms into the processor while maintaining the implemented hardware.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.897-900
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• 2007

This paper presents a study on the DSP controller and IGBT inverter driver design for the power-by-wire(PBW) system using BLDC servo motor. This BLDC servo motor system was realized with DSP(Digital Signal Processor) and IGBT inveter module. The PBW system needs speed control of servo motor for linear thrust action. This paper implements a servo controller with vector control and min-max PWM technique. As CPU of controller, TMS320F2812 DSP was adopted because it has PWM(Pulse Width Modulation) waveform generator, A/D(Analog to Digital) converter, SPI( Serial Peripheral Interface) port and many input/output port etc.

• The Journal of the Acoustical Society of Korea
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• v.14 no.5
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• pp.63-73
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• 1995

The conventional acoustic sounds can be synthesized by Frequency Modulation which includes the variation of frequency, amplitude, and modulation index. In this paper the number of variable synthesis parameters are limited to easily implement the existing two carrier FM algorithm by hardware. The DSP(Digital Signal Processor), which is able to carry out the modified algorithm and synthesize 16 sounds at a time, is designed with $0.8{\mu}m$ standard sells. The DSP which can synthesize 2 sounds at a time is implemented by ASIC emulator to examine the sound quality of the designed DSP. Through the objective and subjective estimation, it is confirmed that the sounds of many instruments from the implemented DSP are very closed to their real sound. Finally the designed DSP is layouted and simulated by VLSI desgn tool. According to the simulation, the designed DSP has the sufficiently fast speed for synthesizing 16 sounds at a time.