• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.39-42
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• 1998

본 논문에서는 방송용 오디오 기기가 갖는 다채널의 특성과 각 채널에 대한 다양한 신호처리 기능의 특성을 고려하여 다채널 디지털 오디오 신호 처리기의 구조를 제안하고 범용 DSP를 이용하여 실시간 병렬 처리 시스템을 구현하였다. 구현된 시스템은 32비트 부동수소점 DSP를 이용하였으며 스테레오 채널의 48KHz 표본화 주파수를 지원하고 20비트 해상도를 갖는 시스템이다. 다채널 디지털 오디오 신호 처리 시스템의 구조는 디지털 신호 처리 과정을 수행하는 디지털 오디오 데이터 처리 부분과 시스템을 제어하기 위한 제어 정보 처리 부분으로 제안하였다. 이러한 구조에 적합한 실시간 시스템을 구현하기 위해 전체 시스템은 4부분의 모듈로 구성된다.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1991.11a
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• pp.176-184
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• 1991

A realization of a conventional cryptosystem for personal computers using the DSP56001 digital signal processing chip is presented. An improved Lucifer-type algorithm is employed to encrypt, and executed in the DSP56001. The Diffie-Hellman method is employed to generate and distribute the key. The implemented hoard can be plugged in the I/O port of personal computers.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.9 no.4
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• pp.294-300
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• 2009

The neural network with radial basis function is introduced for position tracking control of AC servo drive with the existence of system uncertainties. An adaptive robust term is applied to overcome the external disturbances. The proposed controller is implemented on a high performance digital signal processing DSP TMS320C6713-300. The stability and the convergence of the system are proved by Lyapunov theory. The validity and robustness of the controller are verified through simulation and experimental results

• MALSORI
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• no.65
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• pp.143-152
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• 2008

This paper focuses on the real time implementation of an adaptive multi-rate (AMR) speech codec, that is a standard speech codec of IMT-2000, using the TMS320VC5510. The series of TMS320VC55x is a 16-bit fixed-point digital signal processor (DSP) having low power consumption for the use of mobile communications by Texas Instruments (TI) corporation. After we analyze the AMR algorithm and source code as well as the structure and I/O of 7MS320VC55x, we carry out optimizing the programs for real time implementation. The implemented AMR speech codec uses 55.2 kbyte for the program memory and 98.3 kbyte for the data memory, and it requires 709,878 clocks, i.e. about 3.5 ms, for processing a frame of 20 ms speech signal.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.224-229
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• 2008

In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with $0.18{\mu}m$ CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.685-691
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• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.893-894
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• 2006

DSP based on a 8 bit microprocessor was studied for ECG and PPG signals. Digital filtering has an advantage of reducing hardware components in system-on-chip design. However, low resolution such as in 8 bit data has much difficulties in DSP. We demonstrated a comparable performance of DSP filtering compared with analog filters.

• Journal of Satellite, Information and Communications
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• v.11 no.2
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• pp.14-17
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• 2016

This paper describes the implementation of automatic number-braille converter based on image processing for the blind people. The algorithm is consists of four main steps. First step is binary image conversion of the input image obtained by the camera. the second step is segmentation operation by means of dilation and labelling of the character. Next step is calculation of cross-correlation between segmented text image and pre-defined text-pattern image. The final step is generation of brail output which is relevant to input image. The computer simulation result was showing 91.8% correct conversion rate for arabian numbers which is printed in A4-sheet and practical possibility was also confirmed by using implemented automatic number-braille converter based on DSP image processing board.

• The Journal of the Acoustical Society of Korea
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• v.21 no.7
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• pp.648-655
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• 2002

This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.109-110
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• 2006

The performance of a digital baseband signal processing and data transmission rate depends on the modulation technique. In this paper, We implemented DSP communication system for Underwater acoustic communication using by adaptive BPSK modem technique. In order to implement adaptive modem, we suggested SNR detection block. SNR detection block has the reference SNR value that selects between window filter path and matched filter path. In this paper, suggested system is based on software interface and all Hardware(PLL, modem filter, equalizer etc) is implemented by software, exclusive of DSP, A/D, D/A converter, SDRAM and Flash memory.