• 한국정보통신설비학회:학술대회논문집
• /
• 한국정보통신설비학회 2006년도 하계학술대회
• /
• pp.141-144
• /
• 2006

The personal digital recorder is a consumer electronics device that records television shows to a hard disk in digital format. In this paper, we propose an implementation method of personal digital recorder for HDTV. The proposed personal recorder includes CPU and system control modules, graphics and display module, audio DSP module, digital I/O module, NIM module, graphic software library, and embedded software modules for providing a lot of personal digital recorder functions such as live or reserved recordings, browsing of recorder content list, trick lay and time shifting. Especially, combining trick play with time shifting makes much more convenient functions such as pausing live TV, instant replay of interesting scenes, and skipping advertising.

• 정보학연구
• /
• 제9권1호
• /
• pp.33-39
• /
• 2006

This study is for the contents of development to the hardware system and software driving algorithm to implement the frequency band of about 7KHz los pass digital filter which has the cut-off frequency of 392Hz by interfacing of a microprocessor with its peripheral analog-to-digital converter chip and digital-to-analog converter chip. The simplicity of digital filter design without difficulty and the implementation of programmed digital filter can be realized by providing the interfacing method to implement the law pass digital filter for the biological signals and the realization method of computer algorithm by a microprocessor.

• Journal of Power Electronics
• /
• 제11권2호
• /
• pp.113-119
• /
• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
• /
• pp.619-621
• /
• 2005

This paper proposes apractical design method for ship-to-ship missiles' autopilot. When the pre-designed analogue autopilot is implemented in digital way, theygenerally suffer from severe performance degradation and instability problem even for a sufficiently small sampling time. Also, aerodynamic uncertainties can affect the overall stability and this happens more severely when the nonlinear autopilot is digitally implemented. In order to realize a practical autopilot, two main issues, digital implementation problem and compensation for the aerodynamic uncertainties, are considered in this paper. MIMO (multi-input multi-output) nonlinear autopilot is presented first and the input and output of the missile are discretized for implementation. In this step, the discretization effect is compensated by designing an additional control input. Finally, we design a parameter adaptation law to compensate the control performance. Stability analysis and 6-DOF (degree-of-freedom) simulations are presented to verify the proposed adaptive autopilot.

• 디지털산업정보학회논문지
• /
• 제15권4호
• /
• pp.93-101
• /
• 2019

This paper presents a software design and implementation of software-defined radio based IEEE 802.11ac encoder using Texas Instruments TMS320C6670 digital signal processor (DSP) platform. In this paper, the implemented encoder has the capability of generating all the signals consisting of preamble field and data field under different modulation & coding scheme in the IEEE 802.11ac standard. Moreover, the flexibility in choosing different rate, bandwidth, or mode can also be achieved by software reconfiguration using the DSP. As a result, by utilizing the computing power provided by multi-cores as well as the FFT coprocessors in the DSP, the required maximum throughput 78Mbps can be fully reached within 4 ㎲ for each OFDM symbol in the case of 20MHz bandwidth of IEEE 802.11ac.

• International Journal of Computer Science & Network Security
• /
• 제21권5호
• /
• pp.183-191
• /
• 2021

The advanced development of the world's economies requires a detailed study of the impact of factors on the level of digitalization, to ensure economic growth and promote the use of information and communication technologies in the digital economy. Digitalization of the world's economies is ensured through the implementation of relevant regulations and policy decisions to implement public policy and strategy of the digital economy. The purpose of the study is to establish the pattern of the impact of factors on the level of digitalization of world economies by conducting a regression analysis to reflect the dependence of the impact of factors on the level of digitalization in 25 economies (by IMD digital competitiveness), to check the level of digitalization of the world's economies. It is necessary to analyze the ranking of countries in the world according to the DiGiX Index, IMD, and DESI Digital Competitiveness Rating. Research methods: information synthesis method; regression analysis; systematization, and generalization. Results. It was found that because of regression analysis, the value of the coefficient of determination indicates that the regression model by 78% explains the relationship between future readiness of countries to implement digital technologies and information and communication technologies, but there are still a small number of other factors not included in the regression model. It is determined that the greatest progress among EU member states for the period 2015-2020 according to the DESI index belongs to Ireland, the Netherlands, Malta, and Spain. It is established that Estonia, Spain, and Denmark are in the lead in the DESI rating, in terms of e-government implementation. The study found that the impact of factors on the level of digitalization of world economies contributes to solving current economic problems through further implementation of information and communication technologies and improving legislation in the digital economy, which will ensure the implementation of effective digital policy. It is established that ensuring the appropriate level of digitalization of the world's economies should solve the problems in the digital economy sector faced by governments and businesses, which requires the implementation of measures to regulate and ensure the continued operation of the digital economy.

• 한국통신학회논문지
• /
• 제23권7호
• /
• pp.1718-1731
• /
• 1998

디지탈 quadrature 복조기는 디지탈 통신 시스템에서 변조된 신호의 정확한 위상 복조를 위해 꼭 필요하다. 기존의 방법들은 주로 DDFS(Direct Digital Frequency Synthsizer)를 이용하여 캐리어를 발생시킨 후에 승산기를 이용하여 복조를 수행하였다. 그리고, DDFS에는 주로 ROM(Read Only Memory)을 사용하였는데, 높은 속도와 정확도를 요구하는 경우 ROM의 속도와 크기가 제한이 될 수있다. 이러한 점을 극복하기 위하여 CORDIC(COordinate Rotation Digital Computer) 알고리듬을 사용하여 주파수 합성은 물론 캐리어 복조까지 수행하는 방식을 제안하였다. 최적의 하드웨어 구현을 위해 제한된 단어길이에 의한 영향을 분석하였으며, 하드웨어 비용면에서 ROM을 사용하는 방법과 비교한 결과 약 1/3 정도로 면적이 줄었다. 제안된 구조를 이요한 전주문형 VLSI 구현 결과를 보인다.

• 디지털콘텐츠학회 논문지
• /
• 제9권2호
• /
• pp.235-244
• /
• 2008

본 논문의 목적은 기존의 디지털자산관리시스템을 비교분석하여 적합한 실행모델을 개발하는데 있다. 본 연구 결과, 적합한 시스템은 아카이빙 서버, 처리 서버, 그리고 인터페이스 시스템으로 구성되는 것이 바람직하다. 이러한 연구결과를 바탕으로 국내실정에 맞는 신뢰성 있고 타당성 있는 디지털미디어자산관리시스템 구축모형을 제안하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권4호
• /
• pp.477-483
• /
• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• 한국통신학회논문지
• /
• 제17권12호
• /
• pp.1371-1379
• /
• 1992

본 논문에서는 디지털 이동통신 시스템에 대하여 전반적으로 소개하고 가장 중요한 기능의 하나인 로우밍 기능 구현을 위한 클라이언트-서버 모델을 제안하고 이에 대한 실험 및 고찰에 대하여 기술한다.