• Title/Summary/Keyword: Digital Frequency Synthesizer

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Design of the Transceiver for a Wide-Range FMCW Radar Altimeter Based on an Optical Delay Line (광 지연선 기반의 넓은 고도 범위를 갖는 고정밀 FMCW 전파고도계 송수신기 설계)

  • Choi, Jae-Hyun;Jang, Jong-Hun;Roh, Jin-Eep
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.11
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    • pp.1190-1196
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    • 2014
  • This paper presents the design of a Frequency Modulated Continuous Wave(FMCW) radar altimeter with wide altitude range and low measurement errors. Wide altitude range is achieved by employing the optic delay in the transmitting path to reduce the dynamic range of measuring altitude. Transmitting power and receiver gain are also controlled to have the dynamic range of the received power be reduced. In addition, low measurement errors are obtained by improving the sweep linearity using the Direct Digital Synthesizer(DDS) and minimizing the phase noise employing the reference clock(Ref_CLK) as the offset frequency of the Phase Locked Loop(PLL).

Design of Voltage Controlled Oscillator Using the BiCMOS (BiCMOS를 사용한 전압 제어 발진기의 설계)

  • Lee, Yong-Hui;Ryu, Gi-Han;Yi, Cheon-Hee
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.11
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    • pp.83-91
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    • 1990
  • VOC(coltage controlled oscillator) circuits are necessary in applications such at the demodul-ation of FM signals, frequency synthesizer, and for clock recovery from digital data. In this paper, we designed the VCO circuit based on a OTA(operational transconductance amplifier) and the OP amp which using a differential amplifier by BiCMOS circuit. It consists of a OTA, voltage contorolled integrator and a schmitt trigger. Conventional VCO circuits are designed using the CMOS circuit, but in this paper we designed newly BiCMOS VCO circuit which has a good drive avlity, As a result of SPICE simulation, output frequency is 141KHz at 105KHz, and sensitivity is 15KHz.

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Implementation of a digital FM composite signal generator (디지털 방식 FM 합성 신호 발생기의 구현)

  • 정도영;김대용;유영갑
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.5
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    • pp.1349-1359
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    • 1998
  • In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

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A Study on Design and Implementation of Hangul-NAVTEX Simulator (한글 NAVTEX시뮬레이터 설계 및 구현에 관한 연구)

  • 이헌택;김기문
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.4
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    • pp.819-830
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    • 1999
  • NAVTEX system is an international automated direct-printing service, broadcast on 5181kHz and 490kHz, for the promulgation of navigational and meteorological warnings and urgent information to ships. With our government's adoption of the international convention for SAR(Search and Rescue) in 1993, various trials for the installation of NAVTEX system have been executed by the government committee, relating laboratory and experts. An important consideration of the installation for NAVTEX system is the availability that could broadcast messages written in korean letter. Also, the receiver which can process the signal demodulated from the two frequencies, 518kHz and 490kHz, should be developed and supplied in domestic. In this paper, the code table and algorithm for conversions between NAVTEX characters and Korean Letters are studied, and signal processing techniques of code conversion are developed. Circuit design and implementation of the NAVTEX simulator using the Direct Digital Synthesizer are discussed, code conversion algorithm and signal processing technique of the NAVTEX transmission are programmed in its circuits. For evaluating the its functional characteristics, receiving module which has I-Q channel structure is designed. From the measurements of simulator, the characteristics show the frequency stability of the $(\pm)2Hz$ and Spurious free dynamic range is -63dBc. And the simulator can generate simultaneously wanted signal and several interfere signals. So, its capability is valuable for designers of the transmitting system and NAVTEX receiver, for provider as testing facilities of the type approval.

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Waveform Generator for W-band Compact Radar (W-band 소형 레이다용 파형발생부)

  • Lee, Man-Hee;An, Se-Hwan;Kim, Young-Gon;Kim, Hong-Rak
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.18 no.5
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    • pp.97-102
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    • 2018
  • In this paper, W-band Waveform Generator for compact radar has been designed and fabricated. DDS (Direct Digital Synthesizer) is applied to generate CW (Continuous Wave) and FMCW (Frequency Modulation Continuous Wave) waveform at high speed. We designed two LO (Local Oscillator) paths for functions of distance delay and distance tracking tests at the prpposed system without extra test equipment. Two mode selections are provided by switch. It is observed that fabricated waveform generator performs -91 dBc/Hz phase noise at offset 1 kHz and -63.2 dBc spurious. Proposed W-band Waveform Generator is expected to apply for W-band compact radar transceiver module.

Design of the 10MHz and 10W Power Source for Short Distance Wireless Power Transmission (근거리 무선 전력 전송을 위한 평형 증폭기 구조의 10MHz 10W급 전력원 설계)

  • Park, Dong-Hoon;Kim, Gui-Sung;Lim, Eun-Cheon;Park, Hye-Mi;Lee, Moon-Que
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.3
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    • pp.437-441
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    • 2012
  • In this paper, we have designed and manufactured 10MHz power source for the application of short distance wireless power transmission. The designed power source consists of a DDS(direct digital synthesizer) signal generator, a buffer driver and a balanced power amplifier. Short range wireless power transmission is usually carried out by near-field inductive coupling between source and load. The distance variation between source and load gives rise to the change of load impedance of power amplifier, which has effect on the operation of power amplifier. To overcome this problem due to load variation of power amplifier, we have adopted the balanced power amplifier using the quadrature hybrid implemented by lumped capacitors and a mutually coupled coil. The experiment results show the above 40dBm output power, frequency range of 9 to 11MHz, and total DC power consumption of 36W.

Design of Regulated Low Phase Noise Colpitts VCO for UHF Band Mobile RFID System (UHF 대역 모바일 RFID 시스템에 적합한 저잡음 콜피츠 VCO 설계)

  • Roh, Hyoung-Hwan;Park, Kyong-Tae;Park, Jun-Seok;Cho, Hong-Gu;Kim, Hyoung-Jun;Kim, Yong-Woon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.964-969
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    • 2007
  • A regulated low phase noise differential colpitts VCO(Voltage Controlled Oscillator) for mobile RFID system is presented. The differential colpitts VCO meets the dense reader environment specifications. The VCO use a $0.35{\mu}m$ technology and achieves tuning range $1.55{sim}2.053 GHz$. Measuring 910 MHz frequency divider output, phase noise performance is -106 dBcMz and -135dBc/Hz at 40 kHz and 1MHz offset, respectively. 5-bit digital coarse-tuning and accumulation type MOS varactors allow for 28.2% tuning range, which is required to cover the LO frequency range of a UHF Mobile RFID system, Optimum design techniques ensure low VCO gain(<45 MHz/V) for good interoperability with the frequency synthesizer. To the author' knowledge, this differential colpitts VCO achieves a figure of merit(FOM) of 1.93dB at 2-GHz band.

A Study on Design and Performance Evaluation of the Frequency Snthesizer Using the DDS in the Transmitter of the FFH/BFSK System (FFH/BFSK 시스템 송신부에서 DDS를 이용한 주파수합성기 설계 및 성능평가에 관한 연구)

  • 이두석;유형렬;정지원;조형래;김기문
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.11a
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    • pp.161-166
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    • 1999
  • The global trends of mobile communication system is moving toward digitizing, high-speed and large-capacity. Also, to utilize the limited frequency-resource efficiently, spread spectrum system is a mainstream. In this study we are concerning with the fast frequency-hopping system. Instead of the PLL with many problems such as phase-noise, we used the DDS is popular in these days minimizes the disadvantage of PLL. In the case the FFH system is designed using the PLL, it is difficult to be satisfied of the design conditions such as RF badwidth and the settling time of PLL, and it has limitation because of complex circuit by using the balanced modulator. In this study, we evaluated the performance in order to design the FFH system using the DDS. The system that has the improvement of error rate, 1Mhps hopping rate and 5MHz RF bandwidth is designed and evaluated.

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Design of a CMOS Tx RF/IF Single Chip for PCS Band Applications (PCS 대역 송신용 CMOS RF/IF 단일 칩 설계)

  • Moon, Yo-Sup;Kwon, Duck-Ki;Kim, Keo-Sung;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.7 no.2 s.13
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    • pp.236-244
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    • 2003
  • In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

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Development of a Multichannel Eddy Current Testing Instrument(I) (다중채널 와전류탐상검사 장치 개발(I))

  • Lee, Hee-Jong;Nam, Min-Woo;Cho, Chan-Hee;Yoon, Byung-Sik;Cho, Hyun-Joon
    • Journal of the Korean Society for Nondestructive Testing
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    • v.30 no.2
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    • pp.155-161
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    • 2010
  • Recently, the electromagnetic techniques of the eddy current testing(ECT), alternating current field testing, magnetic flux leakage testing and remote field testing have been used as a nondestructive evaluation method based on the electromagnetic induction. The eddy current testing is now widely accepted as a NDE method for the heat exchanger tube in the electric power industry, chemical, shipbuilding, and military. The ECT system mainly consists of the synthesizer module, analog module, analog-to-digital converter, power supplier, and data acquisition and analysis program. In this study, the synthesizer module and the analog module which are essential to the ECT system were primarily developed. The developed ECT system is basically a multifrequency type which is able to inject the maximum four frequencies based on the frequency and time domain multiplexing method. Conclusively, we confirmed that the EC signal was processed appropriately in each circuit modules, and the Lissajous EC signal was displayed in the impedance plane.