• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.5
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• pp.71-78
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• 2012

This paper presents a digital control solution to process capacitor current feedback of high performance single-phase UPS for non-linear loads. In all UPS the goal is to maintain the desired output voltage waveform and RMS value over all unknown load conditions and transient response. The proposed UPS uses instantaneous load voltage and filter capacitor current feedback, which is based on the double regulation loop such as the outer voltage control loop and inner current control loop. The proposed DSP-based digital-controlled PWM inverter system has fast dynamic response and low total harmonic distortion (THD) for nonlinear load. The control system was implemented on a 32bit Floating-point DSP controller TMS320C32 and tested on a 5[KVA] IGBT based inverter switching at 11[Khz]. The validity of the proposed scheme is investigated through simulation and experimental results.

• Journal of Digital Convergence
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• v.14 no.9
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• pp.111-121
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• 2016

This study provides an approach to perform the double mediation analysis in structural equation models using the R. For this purpose, the study reviews a variety of techniques for mediation analysis, selects the bootstrapping technique as the most suitable way for performing the double mediation analysis and develops an approach for the double mediation analysis in structural equating models with the bootstrapping using the plspm which is the R package for the performing PLS path analysis. This study will be useful for the studies including the double mediation analysis in structural equation modeling, which is not supported by most of SEM packages, also will provide the knowledge base for in-depth analysis through suggesting the new mediation analysis technique using R for the researchers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.4
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• pp.1-9
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• 2017

In this Paper, Double Encryption Technology Based on Phase-Shifting Digital Holography and Digital Watermarking is Proposed. For the Purpose, we First Set a Logo Image to be used for Digital Watermark and Design a Binary Phase Computer Generated Hologram for this Logo Image using an Iterative Algorithm. And Random Generated Binary Phase Mask to be set as a Watermark and Key Image is Obtained through XOR Operation between Binary Phase CGH and Random Binary Phase Mask. Object Image is Phase Modulated to be a Constant Amplitude and Multiplied with Binary Phase Mask to Generate Object Wave. This Object Wave can be said to be a First Encrypted Image Having a Pattern Similar to the Noise Including the Watermark Information. Finally, we Interfere the First Encrypted Image with Reference Wave using 2-step PSDH and get a Good Visible Interference Pattern to be Called Second Encrypted Image. The Decryption Process is Proceeded with Fresnel Transform and Inverse Process of First Encryption Process After Appropriate Arithmetic Operation with Two Encrypted Images. The Proposed Encryption and Decryption Process is Confirmed through the Computer Simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.613-623
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• 2000

Digital TV tuner for 8-VSB modulation was developed with satisfying the requirements of ATSC. The double frequency conversion and the active tracking filter in the front-end were used to reduce interference of the adjacent channels and multi-channels, which suppress If beat and image band. However, it was impossible to get frequency mapping between tracking filter and first VCO(Voltage Controlled Oscillator) in the double conversion digital TV tuner differing from conventional NTSC tuner. This paper, therefore, suggests the available structure and a new method for automatic frequency selection by obtaining the mapping of frequency characteristic over tracking voltage and the combined hardware which compose of Micro-controller, EEPROM, D/A(Digital-to-Analog Converter), OP amp and switch driver to solve above problems.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.188-198
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• 2010

Recently, as the demand of the environmental-friendly energy storage system such as an electric double-layer condenser increases, that of the bidirectional charger/discharger for the systems also increases. However, when charging/discharging mode-change occurs, the charger/discharger employing a bi-directional DC-DC converter with a commercialized analog controller has a complex circuit scheme, and a poor transient response. On the other hand, if a single digital controller is used for the bi-directional mode, the system performances can be improved by application of an advanced power-processing algorithm. In the paper, an environmental-friendly power storage systems including an Electric Double Layer Capacitor(EDLC) banks were developed with a bi-directional buck-boost converter and a digital signal processor (TMS320F28335). A simulation test-bed was realized and tested by MATLAB Simulink, and the hardware experiment was performed which shows that the dynamic response was improved such as the simulation results.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.6
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• pp.489-497
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• 2001

The proposed dobule phase locked loop and active multiple interphase reactor are used to eliminate the circular current and the voltage ripples caused by the system parameter unbalance of parallel connected UPSs. In this paper, digital controller for the dobule PLL and active interphase reactor is implemented with ADSP21061 as an aspect of functional convenience.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.10
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• pp.141-150
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• 1997

In this paepr, we propose an intelligent double talk detector that can enhance the performance of the acoustic echo cancellation system. The conventional double talk detection methods often misunderstand the echo path changes as double talk. Although there exist several detection methods that can distinguish the echo path changes from the double-talks, they show poor tracking performance because of the excessive decision delay for the discrimination and can only be used after the adaptive digital filter converges. A new and more effective ditetion algorithm has been proposed, where the detection mechanism is performed by observing the change rate of the reflection coefficients of the two lattice predictors that re placed on the near-end and far-end terminals. The excellence of the proposed method is verified by extensive computer simulations using real speech signals.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2013.05a
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• pp.256-257
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• 2013

Roof and exterior wall of general formal buildings are designed and constructed through design focused exterior wall system and drainage and waterproof roof system. However, there are no classification of exterior wall and roof in freeform buildings and they are integrated as a surface of freeform buildings. Therefore it is necessary to develop the dry roof construction method using double skin roof system satisfying the design and function of the envelope. In this study, we have an effort to develop construction method of double-skin roof system using metal panel and PV.