• Title/Summary/Keyword: Digital Audio Amplifier

Search Result 33, Processing Time 0.024 seconds

A High-Efficiency Driver Design for Mobile Digital Audio Speakers (모바일용 디지털 오디오 스피커를 위한 고효율 드라이버 설계)

  • Kim, Yong-Serk;Rim, Min-Joon
    • The Transactions of the Korean Institute of Electrical Engineers P
    • /
    • v.60 no.1
    • /
    • pp.19-26
    • /
    • 2011
  • In this paper, we designed Interpolation FIR(Finite Impulse Response) filter and 1-bit SDM(Sigma- Delta Modulator) for small digital audio speaker, which has low power consumption and high output characteristics. In order to achieve high linearity and low distortion performance of the systems, we adopt Type I Chevychev FIR filter which has equiripple characteristics in the pass band and proposed high efficient FIR filter structure. SDM is the most efficient modulation technique among the noise shaping techniques. In this paper, we implemented SDM using CIFB(Cascade of Intergrators, Feed-Back) which is generally used in DAC of small digital audio speakers. The proposed SDM structure can achieve high SNR, high-efficiency characteristics and low power consumption in mobile devices. Also considering manufacture of SoC(System on Chip), we performed simulation with Matlab and Verilog HDL to obtain optimal number of operational bits and verified a good experimental results.

A Stereo Audio DAC with Asymmetric PWM Power Amplifier (비대칭 펄스 폭 변조 파워-앰프를 갖는 스테레오 오디오 디지털-아날로그 변환기)

  • Lee, Yong-Hee;Jun, Young-Hyun;Kong, Bai-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.7
    • /
    • pp.44-51
    • /
    • 2008
  • A stereo audio digital-to-analog converter (DAC) with a power amplifier using asymmetric pulse-width modulation (PWM) is presented. To adopt class-D amplifier mainly used in high-power audio appliances for head-phones application, this work analyzes the noise caused by the inter-channel interference during the integration and optimizes the design of the sigma-delta modulator to decrease the performance degradation caused by the noise. The asymmetric PWM is implemented to reduce switching noise and power loss generated from the power amplifier. This proposed architecture is fabricated in 0.13-mm CMOS technology. The proposed audio DAC including the power amplifier with single-ended output achieves a dynamic range (DR) of 95-dB dissipating 4.4-mW.

A Class-D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise

  • Lee, Dongjun;Noh, Jinho;Lee, Jisoo;Choi, Yongjae;Yoo, Changsik
    • ETRI Journal
    • /
    • v.35 no.5
    • /
    • pp.819-826
    • /
    • 2013
  • A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulse-code modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-${\mu}m$ CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 ${\mu}W$ from a 1.2-V power supply.

A Digital Input Class-D Audio Amplifier (디지털 입력 시그마-델타 변조 기반의 D급 오디오 증폭기)

  • Jo, Jun-Gi;Noh, Jin-Ho;Jeong, Tae-Seong;Yoo, Chang-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.47 no.11
    • /
    • pp.6-12
    • /
    • 2010
  • A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.

Synchronization Method and Link Level Performance of DMB System A considering HPA Nonlineariry (HPA 비선형성을 고려한 DMB 시스템 A의 링크레벨 성능 및 동기화 기법)

  • Park SungHo;Cha Insuk;Chang KyungHi
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.30 no.6A
    • /
    • pp.488-498
    • /
    • 2005
  • The DAB(Digital Audio Broadcasting) service which is based on the Eureka-147 of Europe is developed to DMB(Digital Multimedia Broadcasting) service that is divided into Terrestrial DMB and Satellite DMB. The Satellite DMB is a new broadcasting service, which will service multi-channel multimedia broadcasting by the portable receiver or the vehicle receiver. In this paper, we consider that link level performance of satellite DMB system A which is based on the COFDM(Coded Orthogonal Division Multiplexing). It uses the OFDM method which is sensitive to nonlinearity, so we analyze the effect of the HPA(High Power Amplifier) nonlinearity. And then we define the appropriate back-off value by performing the link level simulation considering back-off effect. Also we consider the effect of frequency and time offset, and then confirm the overall link level performance by analyzing and verifying a suitable synchronization method for satellite DMB system A.

Implementation of Digital Hearing Aid Using Bluetooth Audio Digital Signal Processor

  • Choi, Mi-Lim;Ahn, Tae-hyun;Paik, Nam-Chil;Kwon, Young-Man;Lim, Myung-Jae;Chung, Dong-Kun
    • International Journal of Internet, Broadcasting and Communication
    • /
    • v.9 no.2
    • /
    • pp.58-63
    • /
    • 2017
  • The sound we hear is transmitted through the atmosphere. However, both the sound we want to hear and the surrounding sound are mixed, and noise is generated, and the sound is not clearly transmitted due to factors such as distance. In particular, in closed spaces like buildings, it is often difficult to hear sounds from outside because of the sound of reflection. People with hearing impairments, such as the elderly and the deaf, have a hard time hearing the sounds they want to hear. Thus, we are developing a hearing aid that can detect radio waves. To this end, we propose the development of a hearing aid that uses FM radio and Bluetooth. These devices are expected to be useful not only for the elderly and the deaf but also in situations where information is transmitted to a large number of people, such as students and tourists, in a large space. The main purpose of this device is to enable users to hear sound correctly without blind spots.

Class-D Digital Audio Amplifier Using 1-bit 4th-order Delta-Sigma Modulation (1-비트 4차 델타-시그마 변조기법을 이용한 D급 디지털 오디오 증폭기)

  • Kang, Kyoung-Sik;Choi, Young-Kil;Roh, Hyung-Dong;Nam, Hyun-Seok;Roh, Jeong-Gin
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.3
    • /
    • pp.44-53
    • /
    • 2008
  • In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

A Study on Design and Implementation of Low Noise Amplifier for Satellite Digital Audio Broadcasting Receiver (위성 DAB 수신을 위한 저잡음 증폭기의 설계 및 구현에 관한 연구)

  • Jeon, Joong-Sung;You, Jae-Hwan
    • Journal of Navigation and Port Research
    • /
    • v.28 no.3
    • /
    • pp.213-219
    • /
    • 2004
  • In this paper, a LNA(Low Noise Amplifier) has been developed, which is operating at L-band i.e., 1452∼1492 MHz for satellite DAB(Digital Audio Brcadcasting) receiver. The LNA is designed to improve input and output reflection coefficient and VSWR(Voltage Standing Wave Ratio) by balanced amplifier. The LNA consists of low noise amplification stage and gain amplification stage, which make a using of GaAs FET ATF-10136 and VNA-25 respectively, and is fabricated by hybrid method. To supply most suitable voltage and current, active bias circuit is designed Active biasing offers the advantage that variations in $V_P$ and $I_{DSS}$ will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets $V_{gs}$ for the desired drain voltage and drain current. The LNA is fabricated on FR-4 substrate with RF circuit and bias circuit, and integrated in aluminum housing. As a reults, the characteristics of the LNA implemented more than 32 dB in gain. 0.2 dB in gain flatness. lower than 0.95 dB in noise figure, 1.28 and 1.43 each input and output VSWR, and -13 dBm in $P_{1dB}$.

An Interpolation Filter Design for the Full Digital Audio Amplifier (완전 디지털 오디오 증폭기를 위한 보간 필터 설계)

  • Heo, Seo-Weon;Sung, Hyuk-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.16 no.2
    • /
    • pp.253-258
    • /
    • 2012
  • A computationally efficient interpolation filter with a low-distortion performance is a key component to utilize the naturally-sampled pulse width modulation (NPWM) in a digital domain. To realize the efficient interpolation filter, we propose a novel design based on the recently-proposed modified Farrow filter. The proposed filter shows a better pass-band distortion performance maintaining similar degree of complexity compared with the conventional Lagrange interpolation filter. We achieve the maximum distortion deviation of 10-3 dB to 20-kHz audible frequency range and distortion reduction of 1/6 times compared with the Lagrange interpolation filter.