• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2006.05a
• /
• pp.961-965
• /
• 2006

Design Up/Down converters which use Digital IF( Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the position If frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.7
• /
• pp.1777-1786
• /
• 1996

This paper describes theories and implementation techniques of a digital high-definition television(HDTV) modem based on 32-QAM for terrestrial broadcasting. We proposed a digital demodulation scheme and a symbol timing recovery structure based on the band edge component maximization(BECM) method. The adaptive equalizer has 256 complex taps to remove the multipath of delays ranging from -2.mu.s~+24.mu.s with a new T/2-spaced blind equalization algorithm. computer simulation results reveal that the proposed algorithm outperforms other conventional blind equalization algorithm a digital HDTV modem with 4.91MHz symobol rate is implemented by utilizing the proposed algorithms. All processings for modem operations such as demodulation, estimation of symbol timing phase error, adaptive equalization, and carrier recovery except IF signal processing and sampling phase control part of the AD converter are done in digital domain. Especially, the carrier recovery loop can track a carrier offset of upto .+-.350KHz.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.2
• /
• pp.173-183
• /
• 1996

In this paper, a new structure that can do fault detection and location of digial logic circuits more efficiently using current testing techniques is proposed. In the conventional method, observation point for steady state power supply current was only one, but in the proposed method more fault classes are divided for fault detection and location through the ovservation of steady state power supply current at two points. Also, it is shown that this structure can be easily applied in detection of stuck-open fault which is not easy to do testing with conventional current testing techniques. In the presented mehtod, an extra trasnistor is used, and current path is made compulsorily in the CMOS circuits in which no current path can be established in steady state, then it can be known that stuck-open tault is in the MOS transistor on the considering current path, if this path disappears due to stuck-open fault. The validity and the effectiveness is shwon, thorugh the SPICE simulation of circuits with fault and the current path search experiment using current path search program based on transistor short model wirtten in C language on SUN sparc workstation.