• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.47-53
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• 2013

In this work, signal transmission properties of SATA connector have been improved using its differential impedance calculation and its design revision to closer impedance matching. Using 3 dimensional electromagnetic field simulator, the differential mode S-parameter was calculated to investigate its signal fidelity. The differential impedance is calculated from the equation of the odd mode impedance with inductance, capacitance, mutual inductance, and mutual capacitance. The differential impedance of SATA connector was calculated to be $107.3{\Omega}$ and did not meet the design specification with $100{\Omega}{\pm}5%$. In order to achieve its impedance range and improve its signal transmission properties, SATA connector's design has been revised with two different directions and analyzed through the calculation of differential impedance, differential reflection loss, and differential insertion loss.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1977-1978
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• 2008

In this paper, we compare performance of common-mode rejection between a differential and a non-differential amplifier system with two electrodes. A differential amplifier system is constant for common-mode rejection ratio(CMRR) on the frequency domain. But a non-differential amplifier's CMRR is determined by $Z_{FB}/Z_e$ ($Z_{FB}$ ; feedback impedance, $Z_e$; electrode impedance). There is trade-off between a non-differential amplifier's CMRR and its differential input impedance. And a non-differential amplifier system has some advantages for a bio-potential measurement with two electrodes because a designer can control the impedance between the body and system's common.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.2
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• pp.193-199
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• 2009

In this paper, impedance analysis of a differential pall having 2 drop configuration is performed using the reflection theory and verified by circuit simulator (Ansoft designer). Through the impedance analysis, it was possible to understand the signal transmission at a differential pall, and an optimized 2 drop design technique of a differential pair could be developed. When compared with the conventional design, the proposed design shows a good signal integrity and has much less design restrictions.

• KEPCO Journal on Electric Power and Energy
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• v.6 no.4
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• pp.473-480
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• 2020

In this paper, we proposed a high frequency equivalent circuit considering parasitic impedance components for differential noise analysis on the input stage during DC-DC buck converter switching operation. Based on the proposed equivalent circuit model, we presented a method to measure parasitic impedance parameters included in DC bus plate, IGBT, and PCB track using the gain phase method of a network analyzer. In order to verify the validity of this model, a DC-DC prototype consisting of a buck converter, a signal analyzer, and a LISN device, and then resonance frequency was measured in the frequency range between 150 kHz and 30 MHz. The validity of the parasitic impedance measurement method and the proposed equivalent model is verified by deriving that the measured resonance frequency and the resonance frequency of the proposed high frequency equivalent model are the same.

• ETRI Journal
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• v.35 no.5
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• pp.827-837
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• 2013

In this paper, we present wideband common-mode (CM) noise suppression using a vertical stepped impedance electromagnetic bandgap (VSI-EBG) structure for high-speed differential signals in multilayer printed circuit boards. This technique is an original design that enables us to apply the VSI-EBG structure to differential signals without sacrificing the differential characteristics. In addition, the analytical dispersion equations for the bandgap prediction of the CM propagation in the VSIEBG structure are extracted, and the closed-form expressions for the bandgap cutoff frequencies are derived. Based on the dispersion equations, the effects of the impedance ratio, the EBG patch length, and via inductances on the bandgap of the VSI-EBG structure for differential signals are thoroughly examined. The proposed dispersion equations are verified through agreement with the full-wave simulation results. It is experimentally demonstrated that the proposed VSI-EBG structure for differential signaling suppresses the CM noise in the wideband frequency range without degrading the differential characteristics.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.3
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• pp.176-182
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• 2021

This research proposes a high-frequency circuit that can accurately predict the differential mode noise of single-phase inverters at the circuit design stage. Proposed single-phase inverter high frequency circuit in the work is a form in which harmonic impedance components are added to the basic single-phase inverter circuit configuration. For accurate noise prediction, parasitic components present in each part of the differential noise path were extracted. Impedance was extracted using a network analyzer and Q3D in the measurement range of 150 kHz to 30 MHz. A high-frequency circuit model was completed by applying the measured values. Simulations and experiments were conducted to confirm the validity of the high-frequency circuit. As a result, we were able to predict the resonance point of the differential mode voltage extracted as an experimental value with a high-frequency circuit model within an approximately 10% error. Through this outcome, we could verify that differential mode noise can be accurately predicted using the proposed model of the high-frequency circuit without a separate test bench for noise measurement.

• ETRI Journal
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• v.37 no.3
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• pp.637-645
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• 2015

Common-mode noise (CMN) is an unresolved problem in wireless capsule endoscopy (WCE) systems. In a WCE system, CMN originates from various electric currents found within the human body or external interference sources and causes critical demodulation performance degradation. The differential operation, a typical method for the removal of CMN rejection, can remove CMN by subtracting two signals simultaneously received by two reception sensors attached to a human body. However, when there is impedance mismatching between the two reception sensors, the differential operation method cannot completely remove CMN. Therefore, to overcome this problem, we propose an enhanced CMN rejection method. The proposed method performs not only subtraction but also addition between two received signals. Then a CMN ratio can be estimated by sufficient accumulation of division operation outcomes between the subtraction and addition outputs during the guard period. Finally, we can reject the residual CMN by combining the subtraction and addition outputs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.423-429
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• 2013

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.9
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• pp.446-450
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• 2000

A conventional variable percentage current differential relaying algorithm for bus protection may misoperate for external faults with severe CT saturation and internal faults with high impedance. This paper proposes a percentage differential current relaying algorithm for bus protection combined with a compensating algorithm of secondary currents of CTs. Even though CTs are saturated and their secondary currents are severely distorted, the proposed relaying algorithm does not only misoperate for external faults with CT saturation but also detects the internal faults with high fault impedance. Thus, the method improves the sensitivity of the relays and does not require any counterplan for CT saturation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.937-942
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• 2013

Equivalent series impedance of high-voltage pulsed power capacitor is one of the important electrical characteristics both for users and for capacitor manufacturers because it may have serious effects on the performance of pulse forming circuits. In this paper, definition of equivalent series impedance and factors which generate equivalent series impedance are reviewed. Theoretical analysis for the calculation of equivalent series impedance based on differential measurement method is described and calculation program has been developed. In order to acquire data which are necessary to calculate equivalent series impedance from discharging current waveform, charging-dischargig controller has been manufactured. Measurement results of equivalent series impedance for high voltage pulsed power capacitor have been given.