• KIEE International Transactions on Electrophysics and Applications
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• 제2C권6호
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• pp.281-286
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• 2002

The temperature accelerated dielectric breakdown strength of on-wafer low-k dielectric polymer films with thicknesses ranging from 94 nm to 1141 nm is investigated by using the current-voltage characteristic measurements with MIS structures. The temperature dependence of dielectric strength is demonstrated to be Arrhenious for all thicknesses. However, the activation energy is found to be strongly thickness dependent. It follows an exponential relationship rather than being a single value, i.e., the activation energy increase significantly as film thickness increases for the thickness below 500 nm, but it is almost constant for the thickness above 500 nm. This relationship suggests that the change of the activation energy corresponding to different film thickness is closely related to the temperature dependence of the electron trapping/detrapping process in polymer thin films, and is determined by both the trapping rate and the detrapping rate. Thinner films need less energy to form a conduction path compared to thicker films. Hence, it leads to smaller activation energy in thinner films, and the activation energy increases with the increase in film thickness. However, a nearly constant value of the activation energy is achieved above a certain range of film thickness, indicating that the trapping rate and detrapping rate is almost equal and eventually the activation energy approaches the value of bulk material.

• 한국진공학회지
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• 제18권6호
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• pp.453-458
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• 2009

SiOC 박막을 BTMSM과 산소의 혼합가스를 사용하여 CVD 방법으로 증착하였다. 박막의 특성은 가스 유량비에 따라서 변하였다. 유전상수는 MIS 구조를 이용하여 C-V 측정법에 의하여 얻었다. 결합의 말단을 구성하는 Si-$CH_3$ 결합 사이의 공간효과에 의해서 기공이 만들어지며, 기공의 형성에 의해서 박막의 두께가 증가하였다. 그러나 분극의 감소에 의해서 만들어지는 SiOC 박막은 두께가 감소하면서 유전상수도 감소되었다. 열처리 후 유전상수는 수산기의 기화에 의해서 감소되었다. 박막의 두께는 분극의 감소에 의한 유전상수의 감소와 연관이 있었다. 굴절률은 박막의 두께에 반비례하는 경향성이 있으며, 박막의 두께와 굴절률의 경향성은 열처리 후에도 변하지 않았다.

• Journal of information and communication convergence engineering
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• 제9권2호
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• pp.217-219
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• 2011

As silicon devices shrink and their density increases, the low dielectric constant materials instead of $SiO_2$ film is required. SiOC film as low-k films was deposited by the capacitively coupled plasma chemical vapor deposition and then annealed at $300{\sim}500^{\circ}C$ to find out the properties of the dependence on the temperature and polarity. This study researched the dielectric constant using by the structure of the metal/SiOC film/p-Si, chemical shift, thickness, refractive index and hardness. The trend of reflective index was inverse proportioned the thickness, but the dielectric constant was proportioned it. The dielectric constant decreased with decreasing the thickness and the increment of the refractive index.

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.145-151
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• 1994

The multi-dielectric layer SiOz/Si3N4/SiO2(ONO) is used to scale down the memory device. In this paper, the change of composition in ONO layer due to the process condition and the conduction mechanism are observed. The composition of the oxide film grown through the oxidation of nitride film is analyzed using auger electron spectroscopy(AES). AES results show that oxygen concentration increases at the interface between oxide and nitride layers as the thickness -of the top oxide layer increases. Results of I-V measurement show that the insulating properties improve as the thickness of the top oxide layer increases. But when the thickness of the nitride layer decreases below 63.angs, insulating peoperties of film 28.angs. of top oxide and film 35.angs. turn over showing that insulating property of film 28.angs. of top oxide is better than that of film 35.angs. of top oxide. This phenomenon of turn over is thought as the result of generation of surface state due to oxygen flow into nitride during oxidation process. As the thickness of the top oxide and nitride increases, the electrical breakdown field increases, but when the thickness of top oxide reaches 35.angs, the same phenomenon of turn over occurs. Optimum film thickness for scaled multi-layer dielectric of memory device SONOS is estimated to be 63.angs. of nitride layer and 28.angs. of top oxide layer. In this case, maximum electrical breakdown field and leakage current are 18.5[MV/cm] and $8{\times}{10^-12}$[A], respectively.

• 한국전기전자재료학회논문지
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• 제26권6호
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• pp.429-433
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• 2013

PTFE composites for use of microwave substrate were fabricated by impregnation and heat treatment fabrication with glass fabric. This study shows dielectric properties such as dielectric constant and loss can be controlled by thickness of PTFE composite with change of pressure condition in heating press process. The dielectric constant of the PTFE composites has decreasing tendency as given higher pressure condition. The dielectric loss has similar result too. Especially, the case of the dielectric loss was affected by the condition of pressure at heating press and had the best performance under 3 MPa. In order to see the reason why thickness conditions make different, their microstructures were also observed.

• Composites Research
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• 제27권1호
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• pp.25-30
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• 2014

실리콘 KE-12, NBR 그리고 NR 등의 유전 탄성체 종류, 두께 및 희석제 함유량을 함수로 한 전기활성 유전탄성체(EADE) 구동 성능에 대해 연구하였다. 탄성체의 두께($1{\rightarrow}0.5{\rightarrow}0.25{\rightarrow}0.1{\rightarrow}0.05$ mm)의 감소에 따라 그리고 희석제의 함유량 증가에 따라 KE-12 탄성체의 작동변위는 증가하였지만, 유전파괴는 낮은 전압에서 발생되었다. 동일한 탄성체 두께(1 mm)에 대해서 KE-12의 변위(2.24 mm)는 동일한 전압(25 kV)에서 NBR 혹은 NR보다 더 높게 나타났다. 시험한 탄성체 종류 중 KE-12는 가장 낮은 탄성계수를 NBR은 가장 높은 탄성계수 나타냈다. 하지만, NBR 탄성체의 변위는 높은 유전상수 때문에 NR의 경우 보다 높았다. EADE 구동기의 중요한 요소는 탄성체의 두께, 탄성계수 및 유전상수임을 확인하였다.

• 대한전자공학회논문지TC
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• 제40권4호
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• pp.54-59
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• 2003

본 논문에서는 유전체 클래드를 갖는 원통형 유전체 공진 안테나를 설계하고 해석하였다. 우선 원통형 유전체의 파동 방정식으로부터 단일 원통형 유전체 공진 안테나의 설계 제원을 산출하였다. 다음으로 유전체 클래드의 영향은 클래드의 두께와 유전율 값을 이용하여 해석하였다. 그 결과 유전체 클래드의 외부 반경 대 원통형 유전체의 반경비 b/a를 1.3으로 하고 클래드의 상대 유전율 값을 내부 유전체의 1/3로 선정하였을 때, 비대역폭이 49%로 기존 안테나보다 2.3배 정도 개선되었다. 그러나 유전체 클래드의 두께와 상대 유전율 값의 변화에 따른 방사 패턴, 빔폭 및 이득 등에는 큰 영향이 없었다.

• 한국표면공학회지
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• 제56권3호
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• pp.169-179
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• 2023

This work studies dielectric breakdown behavior of AAO (anodic aluminum oxide) films formed on pure aluminum at a constant current density in 5 ~ 20 vol.% sulfuric acid (SA) and 2 ~ 8 wt.% oxalic acid (OA) solutions. It was observed that dielectric breakdown voltage of AAO film with the same thickness increased with increasing concentration of both SA and OA solutions up to 15 vol.% and 6 wt.%, respectively, above which it decreased slightly. The dielectric breakdown resistance of the OA films appeared to be superior to that of SA films. After dielectric breakdown test, cracks and a hole were observed. The crack length increased with increasing SA film thickness but it did not increase with increasing OA film thickness. To explain the reason why shorter cracks formed on the OA films than the SA films after dielectric breakdown test, the generation of tensile stresses at the oxide/metal interface was discussed in relation to porosity of AAO films obtained from cross-sectional morphologies.

• Transactions on Electrical and Electronic Materials
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• 제4권4호
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• pp.13-17
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• 2003

This paper deals with the edge effect in thin insulating films, focusing on their dependence on film thickness. The finding is that the electric field is lowered at the edge as the film thickness is reduced, which, in turn, is closely related to dielectric breakdown voltage. In order to analyze this phenomenon, a simple capacitor model is introduced with which dependence of dielectric breakdown voltage around the electrode edge on the film thickness is explained. Due to analytical difficulty to get the expression of electrical field strength at the edge, an equivalent circuit approach is used to find the voltage expression first and then the electric field expression using it. The relation gets to an agreement with the experimental findings shown in the paper. This outcome may be extended to solve similar problems in multi-layer insulating films.

• 한국표면공학회지
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• 제33권4호
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• pp.217-221
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• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.