• Korean Journal of Materials Research
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• v.11 no.11
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• pp.960-964
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• 2001

$Bi_{3.99}Ti_{2.97}V_{0.03}O_{12}$ (BTV) thin films with 3 mol% vanadium doping were Prepared on $Pt/Ti/SiO_2/Si$ substrate by sol-gel method. X-ray diffraction analysis indicated that single-phase layered perovskite were obtained and preferred orientation was not observed. Under the annealing temperature at $600^{\circ}C$, the surface morphology of the BTV thin films had fine-rounded particles and then changed plate-like at $650^{\circ}C$ and $700^{\circ}C$. The remanent polarization $(2P_r)$ and coercive field $(2E_c)$ of $700^{\circ}C$ annealed BTV thin film were 25 $\mu$C/cm$^2$ and 116 kV/cm, respectively. In addition, BTV thin film showed little polarization fatigue during $10_9$ switching cycles. These improved ferroelectric properties were attributed to the increased rattling space and reduced oxygen vacancies by substitution $Ti^{4+}$ ion (68 pm) with smaller $V^{5+}$ ion (59 pm). The dielectric constant and loss were measured 130 and 0.03 at 10 kHz, respectively.

• Korean Journal of Materials Research
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• v.2 no.1
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• pp.43-51
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• 1992

Thin films of )$Pb(Zr, \;TiO_3$ are fabricated by MOCVD using ultrasonic spraying. The films having perovskite structure are made at low deposition temperature, $300-450^{\circ}C$. The phase and composition of the films vary with the composition of the starting solution and the deposition temperature. Dielectric constant of the films is 187 at 1MHz. Ferroelectric hysterysis loop measurements indicate a remanant polarization of $5.5{\mu}C/cm^2$, and coercive field of 65kV/cm. Resistivity of thin films is about $10^{11}{\Omega}cm$ and the breakdown electric field abort 35kV/cm.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.23-23
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• 2011

Chemical-Mechanical Planarization (CMP) 공정이란 화학적 반응 및 기계적인 힘이 복합적으로 작용하여 표면을 평탄화하는 공정이다. 이러한 CMP 공정은 반도체 산업에서 회로의 고집적화와 다층구조를 형성하기 위하여 도입되었으며 반도체 제조를 위한 필수공정으로 그 중요성이 강조되고 있다. 특히 최근에는 Inter-Level Dielectric (ILD)의 형성과 Shallow Trench Isolation (STI) 공정에서실리콘 산화막을 평탄화하기 위한 CMP 공정에 대해 연구가 활발히 이루어지고 있다. 그러나 CMP 공정 후 scratch, pitting corrosion, contamination 등의 Defect가 발생하는 문제점이 존재한다. 이 중에서도 scratch는 기계적, 열적 스트레스에 의해 생성된 패드의 잔해, 슬러리의 잔유물, 응집된 입자 등에 의해 표면에 형성된다. 반도체 공정에서는 다양한 종류의 실리콘 산화막이 사용되고 gks이러한 실리콘 산화막들은 종류에 따라 경도가 다르다. 따라서 실리콘 산화막의 경도에 따른 CMP 공정 및 이로 인한 Scratch 발생에 관한 연구가 필요하다고 할 수 있다. 본 연구에서는 scratch 형성의 거동을 알아보기 위하여 boronphoshposilicate glass (BPSG), plasma enhanced chemical vapor deposition (PECVD) tetraethylorthosilicate (TEOS), high density plasma (HDP) oxide의 3가지 실리콘 산화막의 기계적 성질 및 이에 따른 CMP 공정에 대한 평가를 실시하였다. CMP 공정 후 효율적인 scratch 평가를 위해 브러시를 이용하여 1차 세정을 실시하였으며 습식세정방법(SC-1, DHF)으로 마무리 하였다. Scratch 개수는 Particle counter (Surfscan6200, KLA Tencor, USA)로 측정하였고, 광학현미경을 이용하여 형태를 관찰하였다. Scratch 평가를 위한 CMP 공정은 실험에 사용된 3가지 종류의 실리콘 산화막들의 경도가 서로 다르기 때문에 동등한 실험조건 설정을 위해 동일한 연마량이 관찰되는 조건에서 실시하였다. 실험결과 scratch 종류는 그 형태에 따라 chatter/line/rolling type의 3가지로 분류되었다 BPSG가 다른 종류의 실리콘 산화막에 비해 많은 수에 scratch가 관찰되었으며 line type이 많은 비율을 차지한다는 것을 확인하였다. 또한 CMP 공정에서 압력이 증가함에 따라 chatter type scratch의 길이는 짧아지고 폭이 넓어지는 것을 확인하였다. 본 연구를 통해 실리콘 산화막의 경도에 따른 scratch 형성 원리를 파악하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.32-32
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• 2009

Silicon carbide (SiC) is a wide-bandgap semiconductor that has materials properties necessary for the high-power, high-frequency, high-temperature, and radiation-hard condition applications, where silicon devices cannot perform. SiC is also the only compound semiconductor material. on which a silicon oxide layer can be thermally grown, and therefore may fabrication processes used in Si-based technology can be adapted to SiC. So far, atomic force microscopy (AFM) has been extensively used to study the surface charges, dielectric constants and electrical potential distribution as well as topography in silicon-based device structures, whereas it has rarely been applied to SiC-based structures. In this work, we investigated that the local oxide growth on SiC under various conditions and demonstrated that an increased (up to ~100 nN) tip loading force (LF) on highly-doped SiC can lead a direct oxide growth (up to few tens of nm) on 4H-SiC. In addition, the surface potential and topography distributions of nano-scale patterned structures on SiC were measured at a nanometer-scale resolution using a scanning kelvin probe force microscopy (SKPM) with a non-contact mode AFM. The measured results were calibrated using a Pt-coated tip. It is assumed that the atomically resolved surface potential difference does not originate from the intrinsic work function of the materials but reflects the local electron density on the surface. It was found that the work function of the nano-scale patterned on SiC was higher than that of original SiC surface. The results confirm the concept of the work function and the barrier heights of oxide structures/SiC structures.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.56-56
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• 2003

BaTiO$_3$, SrTiO$_3$단일막과 BaTiO$_3$ (BTO)/SrTiO$_3$ (STO) 산화물 인공격자를 pulsed laser deposition (PLD) 법에 의해서 100 nm 두께의 (La,Sr)CoO3 (LSCO) 산화물 전극이 코핑된 MgO 단결정 기판 위에 증착시켰다. 이러한 기판위에서 2 unit cell의 적층 두께를 갖는 BTO/STO 초격자 (=BTO2/STO2)를 100～5 nm까지 변화시켰다. 또한 BTO와 STO 단일막도 같은 두께로 변화시켰다. 이러한 두께 범위에서 BTO, STO 단일막과 초격자의 격자변형에 따른 유전특성을 살펴 보았다. 두께 변화에 따른 단일막과 초격자의 구조 분석은 포항 방사광 가속기의 x-ray 회절에 의해서 이루어졌다. 다양한 두께를 갖는 BTO2/STO2 초격자에서 BTO와 STO 충은 in-plane 방향으로 격자정합을 유지하면서 변형되었다. 두께가 얇아지면서 하부 LSCO영향으로 BTO, STO의 n-plane 격자상수는 LSCO 격자상수 쪽으로 접근하였다. Out-of-plane 방향의 BTO 격자상수는 두께가 얇아지면서 증가하였고 반면에 STO 격자상수는 감소하였다. STO와 BTO 단일막의 격자변형은 두께가 얇아지면서 in-plane 방향으로 압축응력으로 인해 증가하였다. 그러나, 격자부정합도가 큰 BTO격자에서 더 많이 변형되었다. 또한 초격자에서 BTO격자가 BTO 단일막보다 더 많이 변형되었는데 초격자에서는 BTO, STO 두 층의 발달된 변형뿐만 아니라 하부 LSCO/MgO 기판의 영향을 함께 받고 있기 때문이다. 초격자와 단일막의 유전상수를 살펴보면은 두께가 감소하면서 유전상수가 감소하는 size effect을 보이고 있다. 하지만 초격자에서의 유전상수가 단일막보다 우수한 유전특성을 보이고 있다. 이러한 결과로 볼 때 격자변형이 size effect 영향을 끼치는 중요한 요소임을 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.116-120
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• 2011

The 0.98 ($Na_{0.44}K_{0.52})Nb_{0.84}O_3-0.02Li_{0.04}$ ($Sb_{0.06}Ta_{0.1})O_3-0.5$ mol%CuO ceramics have been fabircated by ordinary sintering technique and the effect of various calcination method on the electrical propertis and microstructure have been studied. It was observed that the various calcination method influenced the elelctrical properties and structural properties of the 0.98NKN-0.02LST-0.5 mol%CuO ceramics with the optimum piezoelectric constant ($d_{33}$) and electromechanical coupling factor ($k_p$) at room temperature of about $155{\rho}C/N$ and 0.349, respectively, from 0.98NKN-0.02LST-0.5 mol%CuO ceramics sample. The curie temperature ($T_c$) of this ceramic was found at $440^{\circ}C$. The 0.98NKN-0.02LST-0.5 mol%CuO ceramics are a promising lead-free piezoelectric ceramics.

• The Journal of the Acoustical Society of Korea
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• v.23 no.2
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• pp.103-108
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• 2004

In this paper, all the materials constants of the PMN-32%PT single crystals grown by the solid state crystal growth method were measured by the resonance method. PMN-PT crystals of tetragonal symmetry have six elastic constants, three piezoelectric constants and two dielectric constants for their independent material constants. These materials constants were extracted from six sets of crystal samples of each different geometry to have different vibration modes respectively. Measured results showed that the crystal has larger electromechanical coupling factor k/sub 33/ (∼86%) and piezoelectric constant d/sub 33/ (∼1200pC/N) than conventional piezoceramics. Validity of the measurement was confirmed through comparison of the results with the impedance spectrum from finite element analysis of the samples and the results measured with a commercial do meter.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• Applied Science and Convergence Technology
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• v.24 no.3
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• pp.53-59
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• 2015

The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on $SiO_2$/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the $SiO_2$ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/$SiO_2$ substrate. Both p-type and n-type graphene on the patterned SAM/$SiO_2$ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid ($BmimPF_6$) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.

• Korean Journal of Materials Research
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• v.5 no.1
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• pp.3-11
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• 1995

$(TiO_{2})$ thin films were deposited on p-Si(100) substrate by APMOCVD using titanium isopropoxide as a source material. The deposition mechanism was well explained by the simple boundary layer theory and the apparent activation energy of the chemical reaction controlled process was 18.2kcal /mol. The asdeposited films were polycrystalline anatase phase and were transformed into rutile phase after postannealing. The postannealing time and the film thikness as well as the postannealing temperature also affected the phase transition. The C-V plot exhibited typical charateristics of MOS diode, from which the dielectric constant of about 80 was obtained. The capacitance of the annealed film was decreased but those of the Nb or Sr doped films were not changed. I-V characteristics revealed that the conduction mechanism was hopping conduction. The postannealing and the doping of Nb or Sr cause to decrease the leakage current and to increase the breakdown voltage.