• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1456-1464
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• 2007

The research of skin-tone detection has been conducting continuously to enlarge the importance in security, surveillance and administration of the information and 'Password Control System' for using face and skin recognition in airports, harbors and general companies. As well as tile rapid diffusion of the application range in image communications and an electron transaction using wide range of communication network, the importance of the accurate detection of skin color has been augmenting recently. In this paper, it will set up the boundaries of skin colors using the information of Cb and Cr in YCbCr color model of human skin color which is from hundreds compiled portrait images for each race, and suggest a efficient yet simple structure about the skin detection which has been followed by whether the comprehension of the boundaries of skin or not with adaptive skin-range set. With the possibility of the 1D Processes which does not use any memory, it is able to be applied to relatively small-sized hardware and system such as mobile apparatuses. To add the selective mode, it is not only available the improvement of tie skin detection, but also showing the correspondent results about previous face recognition technologies using complicated algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.