• Journal of the Korea institute for structural maintenance and inspection
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• v.18 no.6
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• pp.60-71
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• 2014

Cable-stayed bridge, which is one of the representative long-spanned bridge, needs prompt maintenances when a stay cable is damaged because it may cause structural failure of the entire bridge. Many researches are being conducted to develop abnormal behavior detection algorithms for the purpose of shortening the reaction time after the occurrence of structural damage. To improve the accuracy of the damage detection algorithm, ample observation data from various kinds of damage responses is needed. However, it is difficult to measure an abnormal response by damaging an existing bridge, numerical simulation can be an effective alternative. In most previous studies, which simulate the damage responses of a cable-stayed bridge, the damages has been considered as a load variation without regard to its stiffness variation. The analyses of using these simplification could not calculate exact responses of damaged structure, though it may reserve a sufficient accuracy for the purpose of bridge design. This study suggests Gradual Bilinear Method (GBM) which simulate the damage responses of cable-stayed bridge considering the stiffness and mass variation, and develops an analysis program. The developed program is verified from the responses of a simple model. The responses of a existing cable-stayed bridge model are analyzed with respect to the fracture delay time and damage ratio. The results of this study can be used to develop and verify the highly accurate abnormal behavior detection algorithm for safety management of architecture/large structures.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.2
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• pp.218-224
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• 2012

Recently, as the needs of developing the micro autonomous underwater vehicle (AUV) are increasing, the acquisition of the elementary technology is urgent. While they mostly utilizes information of the forward looking sonar (FLS) in conventional studies of the local path control as an elementary technology, it is desirable to use the obstacle avoidance sonar (OAS) because the size of the FLS is not suitable for the micro AUV. In brief, the local path control system based on the OAS for the micro AUV operates with the following problems: the OAS offers low bearing resolution and local range information, it requires the system that has reduced power consumption to extend the mission execution time, and it requires an easy design procedure in terms of its structures and parameters. To solve these problems, an intelligent local path control algorithm based on the beam modeling of OAS with the evolution strategy (ES) and the fuzzy logic controller (FLC), is proposed. To verify the performance and analyze the characteristic of the proposed algorithm, the course control of the underwater flight vehicle (UFV) is performed in the horizontal plane. Simulation results show that the feasibility of real application and the necessity of additional work in the proposed algorithm.

• Journal of the Earthquake Engineering Society of Korea
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• v.6 no.2
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• pp.63-71
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• 2002

This paper examines the ASCE first generation benchmark problem for a seismically excited cable-stayed bridge, and proposes a new semi-active control strategy focusing on inclusion of effects of control-structure interaction. This benchmark problem focuses on a cable-stayed bridge in Cope Girardeau, Missouri, USA, for which construction is expected to be completed in 2003. Seismic considerations were strongly considered in the design of this bridge due to the location of the bridge in the New Madrid seismic zone and its critical role as a principal crossing of the Mississippi River. In this paper, magnetorheological(MR) fluid dampers are proposed as the supplemental damping devices, and a clipped-optimal control algorithm is employed. Several types of dynamic models for MR fluid dampers, such as a Bingham model, a Bouc-Wen model, and a modified Bouc-Wen model, are considered, which are obtained from data based on experimental results for full-scale dampers. Because the MR fluid damper is a controllable energy-dissipation device that cannot add mechanical energy to the structural system, the proposed control strategy is fail-safe in that bounded-input, bounded-output stability of the controlled structure is guaranteed. Numerical simulation results show that the performance of the proposed semi-active control strategy using MR fluid dampers is quite effective.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.59-67
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• 2016

A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.9
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• pp.1-8
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• 2010

A digital phase wrapping modulation (DPM) open-loop polar transmitter can be efficiently applied to a wideband orthogonal frequency division multiplexing (OFDM) communication system by converting in-phase and quadrature signals to envelope and phase signals and then employing the signal mapping process. This mapping process is very similar to quantization in a general communication system, and when taking into account the error that appears during mapping process, one can replace the coordinates rotation digital computer (CORDIC) algorithm in the coordinate conversion part with the Taylor series approximation method. In this paper, we investigate the application of the Taylor series approximation to the cartesian to polar coordinate conversion part of a DPM polar transmitter for wideband OFDM systems. The conventional approach relies on the CORDIC algorithm. To achieve efficient application, we perform computer simulation to measure mean square error (MSE) of the both approaches and find the minimum approximation order for the Taylor series approximation compatible to allowable error of the CORDIC algorithm in terms of hardware design. Furthermore, comparing the processing speeds of the both approaches in the implementation with FPGA reveals that the Taylor series approximation with lower order improves the processing speed in the coordinate conversion part.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.56-64
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• 2012

A smart grid is the next generation power grid which combines the existing power grid with information technology, so an energy efficient power grid can be provided. In this paper, in order to build an efficient smart grid an AMI system, which gears with the existing home network and provides an user friendly management function, is proposed. The proposed AMI system, which is based on an extended home network, consists of various functional units; smart meters, communication modules, home gateway, security modules, meter data management modules (MDMM), electric power application modules and so on. The proposed home network system, which can reduce electric power consumption and transmit data more effectively, is designed by using IEEE 802.15.4. The extended home gateway can exchange energy consumption information with the outside management system via web services. The proposed AMI system is designed to enable two-way communication between the home gateway and MDMM via the Internet. The AES(Advanced Encryption Standard) algorithm, which is a symmetric block cipher algorithm, is used to ensure secure information exchange. Even though the results in this study could be limited to our experimental environment, the result of the simulation test shows that the proposed system reduces electric power consumption by 4~42% on average compared to the case of using no control.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.432-438
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• 2001

In this paper, after applying Defected Ground Structure(DGS) to DC block, changes of gap and length of λ/4 coupled line are investigated by EM simulation and fabrication. As a result, on condition of the same output with the case using typical DC block, the gap between λ/4 coupled line is widen from 0.1 mm to 0.46 mm by 0.36 mm and the length of λ/4 coupled line gets shorter from 17.7 mm to 13.2 mm by 4.5 mm. Also three type power amplifiers using blocking capacitor, typical DC block and DGS DC block are fabricated and investigated. At first, when S parameter characteristics of each amplifier are considered at frequency band of 3.2 +-0.O5 GHz, every amplifier has similar characteristics of gain and S parameter. Second when the output power of amplifiers is 25 dBm after putting CW signal of 3.2 GHz into three type amplifiers, the difference of dominant signal and 2nd harmonic signal using blocking capacitor, typical DC block and DGS DC block is each -44.83 dBc, -66.84 dBc and -64.33 dBc. Therefore harmonic characteristics of amplifiers using typical DC block and DGS DC block is almost same.

• Journal of electromagnetic engineering and science
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• v.1 no.1
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• pp.73-77
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• 2001

We studied the fabrication of GaAs-based pseudomorphic high electron mobility transistors(PHEMT`s) for the purpose of millimeter- wave applications. To fabricate the high performance GaAs-based PHEMT`s, we performed the simulation to analyze the designed epitaxial-structures. Each unit processes, such as 0.1 m$\mu$$\Gamma$-gate lithography, silicon nitride passivation and air-bridge process were developed to achieve high performance device characteristics. The DC characteristics of the PHEMT`s were measured at a 70 $\mu$m unit gate width of 2 gate fingers, and showed a good pinch-off property ($V_p$= -1.75 V) and a drain-source saturation current density ($I_{dss}$) of 450 mA/mm. Maximum extrinsic transconductance $(g_m)$ was 363.6 mS/mm at $V_{gs}$ = -0.7 V, $V_{ds}$ = 1.5 V, and $I_{ds}$ =0.5 $I_{dss}$. The RF measurements were performed in the frequency range of 1.0~50 GHz. For this measurement, the drain and gate voltage were 1.5 V and -0.7 V, respectively. At 50 GHz, 9.2 dB of maximum stable gain (MSG) and 3.2 dB of $S_{21}$ gain were obtained, respectively. A current gain cut-off frequency $(f_T)$ of 106 GHz and a maximum frequency of oscillation $(f_{max})$ of 160 GHz were achieved from the fabricated PHEMT\\`s of 0.1 m$\mu$ gate length.h.