• 한국정밀공학회지
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• 제13권4호
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• pp.43-52
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• 1996

This paper describes interactive computer procedures for design the forming sequences in cold forging. This system is implemented on the personal computer and its environment is a commercial AutoCAD system. The programming language. AutoLISP, was used for the configuration of the system. Since the process of metal forming can be considered as a transformation of geometry, treatment of the geometry of the part is a key in process planning. To recognize the part section geometry, the section entity representation, the section coordinate-redius representation and the section primitive geometru were adopted. This system includes six major modules such as input module, forging design module, forming sequence design module, die design module, FEM verification module and output module which are used independently or in all. The sequence drawing wigh all dimensions, which includes the dimensional tolerances and the proper sequence of operations, can generate under the environment of AutoCAD. The acceptable forming sequences can be verified further, using the FE simulation.

• 한국의상디자인학회지
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• 제8권2호
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• pp.61-71
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• 2006

The purpose of this study is to present a contents production process for costume design analysis by take advantage of the image media of Chinese historical backgrounds. The production process of contents for lectures on fashion design analysis can be summarized as follows: The contents for the design analysis of Chinese costumes can be divided into major media and supplementary media. Major media can be completed through the processes including the selection of Chinese historical backgrounds. images and media (video, DVD title or VOD), verification of image capture parts, image captures, and applications of PPT files. Supplementary media consist of production of analysis materials for each item and TPO, report preparation methods and discussions, and printed matters to be used at the stage of image comparison and verification. This way, a process applicable to the design analysis of Chinese costumes can be presented.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 춘계종합학술대회
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• pp.345-348
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• 2001

본 논문은 디지털 비디오 방송 컴플라이언트 위성 수신칩에 대한 physical 설계 순서 및 검증에 대한 설계 기술에 관한 것으로서 각각의 설계 순서에 대한 고찰 및 문제점 그리고 물리적 레이아웃에 대한 검증 과정과 그 결과에 대하여 기술하였다.

• 대한전자공학회논문지SD
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• 제43권2호
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• pp.96-104
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• 2006

본 논문에서는 VLSI구현을 위한 CAN 프로토콜 컨트롤러의 최적화된 구조를 제안하였으며, 제안된 구조를 이용하여 VLSI로 구현하였다. 또한 많은 시간이 소요되는 검증의 문제점을 보완하기 위하여 3단계 검증기법을 제안하였으며 이를 통하여 빠른 속도의 검증이 가능하게 되었다. 제안된 구조는 기존의 CAN 프로토콜 컨트롤러보다 적은 사이즈의 게이트 수를 갖고 있을 뿐만 아니라 호스트 프로세서와의 연결이 용이하게 구성되어 있기 때문에 비용 및 효율성에서 장점을 갖고 있고, 제안된 3단계 검증기법은 반복되는 검증의 수를 줄임으로써 최적화된 검증을 수행하도록 구성되어 있기 때문에 빠른 속도의 검증이 가능하다. 설계된 CAN 프로토콜 컨트롤러는 0.35마이크론 CMOS공정을 이용하여 제작되었다.

• 한국군사과학기술학회지
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• 제14권3호
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• pp.388-396
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• 2011

Mission Equipment Package(MEP) system is a collection of avionic components that are integrated to perform the mission of the Korean Utility Helicopter(KUH). MEP system development is classified mission-critical embedded system but KUH MEP system developed including flight-critical data implementation. It is important to establish the good development and verification process for the successful system development. This paper describe the development and verification process in each phase for the KUH MEP system. MEP system design is verified through the qualification test, system failure test and compatibility test in System Integration Laboratory(SIL).

• 대한기계학회논문집A
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• 제30권7호
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• pp.816-825
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• 2006

This paper describes the development of a web-based interference verification system in the mold design process. Although several commercial CAD systems furnish interference verification functions, those systems are very expensive and inadequate to perform collaborative works over the Internet. In this paper, an efficient and precision hybrid interference verification algorithm for the web-based interference verification system over the distributed environment has been studied. The proposed system uses lightweight CAD files produced from the optimally transformed CAD data through ACIS kernel and InterOp. Collaborators related to the development of a new product are able to verify the interference verification over the Internet without commercial CAD systems. The system reduces production cost, errors and lead-time to the market. Validity of the developed system is confirmed through case studies.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.285-288
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• 2004

In this paper, we present a design and experiment of PCI Express core verification model. The model targeting Endpoint core based on Verilog HDL is designed by newly-emerging SystemC, which is a new C++ class library based system design approach. In the verification model, we designed and implemented a SystemC host system model which acted as Root Complex and device driver dedicated to the PCI Express Endpoint RTL core. The verification process is scheduled by scenarios which are implemented in host model. We show that the model is useful especially for verifying the RTL model which has dependencies on system software.

• 한국산업융합학회 논문집
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• 제22권6호
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• pp.785-795
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• 2019

This paper is a study on the modeling of the quantity estimation model for offshore plant Material handling equipment in FEED(Front End Engineering Design) verification stage using system engineering approach which is an engineering design methods. The relevant engineering execution procedure is not systemized although the operation method and Material handling equipment selection with weight and space constraints is a key part of the FEED. Using the system engineering process, the stakeholder requirements analysis process, the system requirements analysis, and the final system architecture design were sequentially performed, and the process developed through the functional development diagram and Requirement traceability matrix (RTM) was verified. In addition, based on the established process, we propose a Material handling quantity estimation model and Quantity calculation verification Table that can be applied at the FEED verification stage and we verify the applicability through case studies.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1013-1016
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• 1998

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

• 한국통신학회논문지
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• 제16권8호
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• pp.793-800
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• 1991

본 연구는, 주민정보시스템에 인감시스템을 추가하여 운용할 수 있도록 설계한 인간조합시스템을 제안하였다. 조합처리의 핵심인 위치정합처리는 원주데이타를 이용했고, 조합판정처리는 XY화소분포를 이용했다. 조합판정실험결과 오조합율이 약 1%였으나, 감산/합산/중첩처리를 통하여 목측판정하므로써 주민관리시스템에 추가하여 운용할 수 있음을 확인했다.