• ETRI Journal
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• v.8 no.1
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• pp.44-52
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• 1986

The main features of HILO-3 logic simulator are introduced. It is regarded as one of the most powerful logic simulator available now in electronic industry. The major functions and concepts are reviewed with some examples; circuit description using HDL (Hardware Description Language), waveform description using WDL (Waveform Description Language) and fault-free simulation for static RAM circuit. This program is expected to help the system designers, integrated circuit designers and test engineers.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1086-1089
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• 1993

The paper deal with the differences between a fuzzy logic controller with a complete linguistic description and one with an incomplete linguistic description. The conditions to get a complete crisp controller by using a fuzzy logic controller with incomplete description are analyzed, and an application to the control of an analog PLL circuit is described, [1].

• Journal of KIISE:Databases
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• v.32 no.2
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• pp.111-119
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• 2005

Electronic catalog contains ich semantics associated with products, and serves as a challenging practical domain for ontology application. Ontology is concerned with the nature and relations of being. It can play a crucial role in e-commerce as a formalization of e-Catalogs. Description Logics provide a theoretical core for most of the current ontology languages. In this paper, we present an ontological model of e-Catalogs in DL. We take an Extended Entity Relationship approach for conceptual modeling method, and present the fundamental set of modeling constructs and corresponding description language representation for each construct. Additional semantic knowledge can be represented directly in DL. Our modeling language stands within SHIQ(d) which is known reasonably practical with regard to its expressiveness and complexity. We illustrate sample scenarios to show how our approach may be utilized in modeling e-Catalogs, and also implement the scenarios through a DL inference tool to see the practical feasibility.

• Journal of the Korean Institute of Gas
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• v.5 no.1
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• pp.37-44
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• 2001

OPS(Operating Procedure Synthesis) systems can reduce the time and effort involved in OPS, make the analysis more thorough and detailed, and minimize or eliminate human errors. And OPS systems capture the expertise needed to create operating procedures and allow this experience to be used in the new situations. But there are the limitations of the OPS techniques that have been used. So in order to resolve this Problem, in this work we have proposed a new approach to utilize temporal constraints and specific process knowledge in temporal logic and description logic. We have demonstrated its remarkable effectiveness in a boiler plant.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.338-346
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• 1987

This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11b
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• pp.700-702
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• 2005

유비쿼터스에 대한 연구에서 지식표현 시스템은 반드시 필요하다. 최근 Description Logic을 많이 사용하고 있는데, Description Logic은 다양한 단계를 표현할 수 있다. 단계가 높아질수록 표현력이 커지는 반면 추론이 어려워진다. 유비쿼터스 환경에서는 서비스를 하기 위해 지식들의 상하위 관계나 동일 관계 등을 추론하는 능력이 필요한데, Description Logic의 단계 중에 ALCUN의 표현력이면 이에 필요한 지식을 모두 표현할 수 있다. 본 논문에서는 ALCUN의 표현력을 지니는 언어를 제안하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.644-646
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• 2003

물류 공급 관리 시스템과 같은 정보 통합 시스템은 분산되어 있는 데이터베이스들에 대해서 정보를 통합하여 사용자에게 보여준다. 이러한 정보 통합 시스템은 전역 질의를 생성하고 지역 질의로 변환하여 실행하기 전에 질의를 최적화할 필요성이 있다. 그런데, 단일데이터 베이스 시스템에서의 질의 최적화 기법은 멀티데이터베이스 시스템에서 사용하기에는 부적절하다. 이는 분산된 데이터베이스 환경에서 오는 높은 연결 오버헤드, 높은 계산 시간, 데이터의 중복성 뿐만 아니라 의미 이질성 문제 때문에 기존의 최적화 방법은 사용하기가 어렵다. 이를 해결하기 위해서 의미상 질의 최적화 방법이 연구되어 왔다. 의미상 질의 최적화는 전역 질의보다 더 효과적으로 응답하고 의미상으로 동등한 질의로 변환하기 위해서 의미상 지식을 사용한다. 본 논문에서는 정보 통합 시스템에서 Description Logic(DL)을 이용하여 의미상 지식으로 사용할 지식 기반을 표현하고 이를 바탕으로 추론화된 지식을 이용하는 의미상 질의 최적화 방식을 제시한다.

• Nuclear Engineering and Technology
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• v.44 no.6
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• pp.697-708
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• 2012

The majority of instrumentation and control (I&C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I&C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I&C systems. Therefore, existing NPPs are replacing the obsolete analog I&C systems with advanced digital systems. New NPPs are also adopting digital I&C systems because the economic efficiencies and usability of the systems are higher than the analog I&C systems. Digital I&C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1577-1580
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• 1987

This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.