• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.565-570
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• 2015

Spread spectrum communications have increased interest due to their immunity to channel fading and low probability of intercept. One of the limitations of the traditional digital spread spectrum systems is the need for spreading code synchronization. Chaotic communication is the analogue alternative of digital spread spectrum systems beside some extra features like simple transceiver structures. In this paper, This paper was used instead of the digital modulation and demodulation carriers for use in the chaotic signal in a digital communication system among the chaotic modulation schemes, the Differential Chaos Shift Keying(DCSK) is the most efficient one because its demodulator detects the data without the need to chaotic signal phase recovery. Also Implementation of Differential Chaos Shift Keying Communication System Using Matlab/Simulink and the receiver con decode the binary information sent by the transmitter, performance curves of DCSK are given in terms of bit-error probability versus signal to noise ratio with spreading factor as a parameter and we compare it to BPSK modulation.

• Journal of Advanced Navigation Technology
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• v.4 no.1
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• pp.36-44
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• 2000

A frequency-shifting technique that uses a digital filter in order to interpolate a bandpass-sampled signal at a low-pass position is investigated. The discussion focuses on the derivation of the required digital filter. It is shown that second-order bandpass sampling offers more flexibility than first-order bandpass sampling in the sense of sampling frequency choice. It is also shown that the well-known quadrature-sampling method for frequency-shifting is a special case of the general second-order sampling technique. The advantages of the mixer-free digital quadrature demodulations are increased flexibility for sampling frequency choice and high precision for I/Q component extraction, and this type of modulation can be applied for modern radar signal processing with high performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3C
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• pp.237-244
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• 2006

I/Q phase unbalance caused by non-ideal circuit components is inevitable physical phenomenons and leads to performance degradation when we implement a practical coherent M-ary phase shift keying(M-PSK) demodulator. In this paper, we present an exact and general expression involving two-dimensional Gaussian Q-functions for the bit error rate(BER) of uniform M-PSK with I/Q phase unbalance over an additive white Gaussian noise(AWGN) channel. First we derive a BER expression for the k-th bit of 8, 16-PSK signal constellations when Gray code bit mapping is employed. Then, from the derived k-th bit BER expression, we present the exact and general average BER expression for M-PSK with I/Q phase unbalance. This result can readily be applied to numerical evaluation for various cases of practical interest in an I/Q unbalanced M-PSK system, because the one- and two-dimensional Gaussian Q-functions can be easily and directly computed using commonly available mathematical software tools.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6A
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• pp.920-930
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• 1999

Many researches on the multi-level QAM(Quadrature Amplitude Modulation) which is known to be a promising digital data transmission method for efficient use of channel bandwidth have been carried on, and their applications to various real fields are now being in progress. However, in the band-limited communication systems, each transmitted symbols is distorted by the ISI(Intersymbol Interference) and the phase error. Therefore, an equalizer and a carrier recovery must be taken into considerations to attenuate the effects of these distortions in the receiver. This paper presents an effective receiver structures that is applicable to the multi-level QAM. The proposed receiver system is consisted of an equalizer with Godard’s blind algorithm and a carrier recovery circuit. The phase error is estimated with a $\theta$-matching algorithm and is used in the carrier recovery to recover the correct phase. The simulation results are included to evaluate performance of the proposed receiver system for the various channel models.

• Journal of IKEEE
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• v.22 no.2
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• pp.432-439
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• 2018

In this paper, an omnidirectional visible light detector was developed by making the detecting surface of a flexible solar cell in a cylindrical form, which has a uniform receiving pattern in the horizontal plane. This solar cell detector receives simultaneously multiple signal lights incident from different directions and provides electrical power to the ASK demodulator in the receiver. In experiments, time division transmission method was used to receive three signal lights incident from different directions to the solar cell detector. Each signal light was ASK modulated using a carrier of 40 kHz, and the synchronizing pulses required for time division transmission were generated by detecting the 120 Hz AC signal included in the indoor illumination lamp with Cds cells. This receiving structure is useful in constructing an $N{\times}1$ optical link in visible light communication.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.21-27
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• 2013

In this paper, we propose a low-complexity Turbo coded BICM-ID (bit-interleaved coded modulation with iterative decoding) system. A Turbo code is a powerful error correcting code with a BER (bit error rate) performance very close to the Shannon limit. In order to increase spectral efficiency of the Turbo code, a coded modulation combining Turbo code with high order modulation is used. The BER performance of Turbo-BICM can be improved by Turbo-BICM-ID using iterative demodulation and decoding algorithm. However, compared with Turbo-BICM, the decoding complexity of Turbo-BICM-ID is increased by exchanging information between decoder and demodulator. To reduce the decoding complexity of Turbo-BICM-ID, we propose a low-complexity Turbo-BICM-ID system. When compared with conventional Turbo-BICM-ID, the proposed scheme not only show similar BER performance but also reduce the decoding complexity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.78-86
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• 2010

This paper discusses the programming model of SODA-II that is a baseband processor for software defined radio (SDR) systems. Signal processing On-Demand Architecture Ⅱ (SODA-II) is an on-chip multiprocessor architecture consisting of four processor cores and each core has both an wide SIMD datapath and a scalar datapath. This architecture is appropriate for baseband processing that is a mixture of vector computations and scalar computations. The programming model of the SODA-II is based on C library routines. Because the library routines hide the details of complex SIMD datapath control procedures, end users can easily program the SODA-II without deep understanding on its architecture. In this paper, we discuss the details of library routines and how these routines are exploited in the implementation of baseband signal processing algorithms. As application examples, we show the implementation result of W-CDMA multipath searcher and OFDM demodulator on the SODA-II.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.79-85
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• 2004

In this paper, the RF-ID system for ubiquitous tagging applications has been designed, fabricated and analysed. The RF-ID System consists of passive RF-ID Tag and Reader. The passive RF-ID tag consists of rectifier using zero-bias schottky diode which converts RF power into DC power, ID chip, ASK modulator using bipolar transistor and slot loop antenna. We suggest an ASK undulation method using a bipolar transistor to compensate the disadvantage of the conventional PIN diode, which needs large current Also, the slot loop antenna with wider bandwidth than that of the conventional patch antenna is suggested The RF-ID reader consist of patch array antenna, Tx/Rx part and ASK demodulator. We have designed the RF-ID System using EM and circuit simulation tools. According to the measured results, The power level of modulation signal at 1 m from passive RF-ID Tag is -46.76 dBm and frequency of it is 57.2 KHz. The transmitting power of RF-ID reader was 500 mW

• Journal of Advanced Navigation Technology
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• v.16 no.5
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• pp.810-816
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• 2012

In this paper, BER(Bit Error Ratio) performances of the TransferJet system, which is the standard of a close proximity inductive wireless communication system, are presented and analyzed. Comparing to other wireless communication systems, the TransferJet system has some advantages such as short communication range(i.e., high security in the wireless communication environments), fewer effects of multipath distortion, and higher transmission rate. In order to demodulate the received signal, either SC(Soft-decision Combining) or HC(Hard-decision Combining) can apply to the despreader and demodulator of the receiver. When the spreading factor is more than 4, the SC scheme approximately has a minimum signal-to-noise ratio gain of 2 dB over the HC scheme. Moreover, from simulation results, we can conclude that the quantization bits of 3 bits are an optimum value for the SC scheme in the TransferJet system since the 3-bit quantization achieves nearly the performance as that attained by double-precision floating-point.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.462-469
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• 2008

In this paper, we design the FPGA (Field-Programmable Gate Array) of the KOINONIA WPAN (Wireless Personal Area Network), and implement the SoC (System on Chip). We use the redundant bits to make a constant-amplitude in a modulator part. Additionally, the SNR (Signal to Noise Ratio) performance of the demodulator is improved by using the redundant bits in decoding steps. The four-million FPGA of the KOINONIA WPAN can be operated at 44MHz frequency. The PER (Packet Error Rate) of the designed FPGA with RF (Radio Frequency) module is below 1% at the -86dB MIPLS (Minimum Input Power Level Sensitivity), and the SNR is about 13dB. The SoC is implemented by using Hynix 0.25um CMOS (Complementary Metal Oxide Semiconductor) process. The size of the SoC is $6.52mm{\times}6.92mm$.