• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.1
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• pp.56-63
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• 2003

This paper studies that torque model considered with decaying phase back-EMF is different In conduction and commutation period and analyzes the torque pulsation components mathematically. In this paper, it is proposed a novel method to suppress torque pulsation due to commutation time. First, it propose commutation delay time control method, which is to compensate current slope of rising phase and decaying phase to control commutation time. Current ripple is minimized at non-commutating current and torque ripple is reduced below critical speed range that dc link voltage is the same as four times of back-EMF voltage. However, torque ripple still exists due to the relation with back-EMF and commutating current and it is increased on a large scale above critical speed range, especially. Secondly, proposed method is commutation time control, which is considered with torque pulsation due to the relation of back-EMF and commutating current. Through the proposed method, the torque pulsation can be minimized in the whole speed range as well as range over critical speed.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.113-119
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• 2006

This paper studies the torque characteristics of CDTP controlled BLDCM with various back-EMF waveforms. We propose a CDTP method to suppress torque pulsation due to commutation time and point. It is adopted to control the BLDCM with real back-EMF waveforms through the Hague's method for minimizing torque ripple. Real back-EMF waveforms are produced with a magnetic fringing factor and crest width of back-EMF. The performance and characteristics of the proposed control method are analyzed by simulation and verified through experimental results.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.4-7
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• 2005

본 논문에서는 역기전력을 고려한 새로운 토크모델인 CDTP(Commutation Delay Time and Point) 제어기법을 이용하여 실제 역기전력을 고려한 BLDC(Brushless DC)전동기의 토크맥동에 대하여 연구하였다. BLCD 전공기의 상전환(Commutation)시 발생하는 토크맥동에 대하여 기술하였으며 토크맥동의 원인이 되는 역기전력과 전류와의 관계를 고찰하였다. 이를 바탕으로 토크맥동의 개선을 위하여 상전환시점과 상전환기간을 고려한 CDTP 제어기법을 제안하였으며 맥동토크의 저감효과에 대하여 해석하였다. 또한 BLDC 전동기의 실제 역기전력을 고려하기 위하여 Hague의 해석방법에 따른 역기전력의 다양한 형태를 살펴보고, 제안한 CDTP기법을 적용하여 기존 방법을 통한 토크맥동 제어방법과 비교 ${\cdot}$ 검토하였다. 이의 검증을 위하여 MATLAB/Simulink를 이용하여 제안한 방식의 토크맥동 저감방법의 타당성을 살펴보았다.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.8
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• pp.157-164
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• 2000

This paper presents a method to detect a rotor position and to drive a BLDC motor from standstill to medium speed without any position sensor comparing the current responses due to the inductance variation in the rotor position. A rotor position at a standstill is identified by the current responses of six pulses injected to each phase of a motor. Once the motor stars up pulse train that is composed of long and short pulses is injected to the phase corresponding to produce the maximum torque and the next phase continuously. it provides not only the torque but also the information of the next commutation time effectively when the response of long and short pulses crosses each other after the same time delay. This method which is verified experimentally using a DSP can drive a BLDC motor to the medium speed smoothly without any rattling and time delay compared with the conventional sensorless algorithm.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.12
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• pp.751-758
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• 2004

This paper presents a new method to compensate the non-linearity for matrix converter drives using PQR instantaneous Power theory. The non-linearity of matrix converter drives such as commutation delay, turn-on and turn-off time of switching device, and on-state switching device voltage drop is modelled by PQR power theory and compensated using a reference current control scheme. The proposed method does not need any additional hardware and off-line experimental measurements. The proposed compensation method is applied for high performance induction motor drives using a 3 kW matrix converter system without a speed sensor. Simulation and experimental results show the proposed method using PQR power theory Provides good compensating characteristic.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1231-1234
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• 2003

Pneumatic servo valve which is widely applied in industrial world is advanced technology compounded with electric, electronic and machine. And It is consist of Linear Force Motor. Spool Commutation Mechanism and Microprocessor. In this study, we accomplished test method of Linear Force motor test, Static characteristic test, Dynamic characteristic test for KS(Koran industrial standard) of Pneumatic servo valve. we accomplished study about the main item of Static characteristic test which is related to unload flow characteristic test. And Dynamic characteristic test was step input test and frequency response test. Specially about frequency response test, There was a difficulty resulting from the time delay problem caused by the basic compressibility of air. In order to solve the problem in this study. we proposed two methods. First, displacement of the servo valve spool was directly measured by using a laser sensor. Second, method of calculating control flow by measuring pressure and temperature of chamber.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.