• Journal of Advanced Marine Engineering and Technology
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• 제26권5호
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• pp.565-572
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• 2002

The design concept of diesel engines for sea-going ships has been directed to Low-speed/Long-Stroke type to improve the efficiencies of combustion and propelling. But time-delay inevitable at low speed gives much difficulties for governors to control the engine speed because they would be apt to go into unstable region especially when operating at low speed. The purpose of this paper is to study the problem of how the governor gain can be calculated dynamically in accordance with the valiance of engine speed to locate the engine still on the properly stable condition. In this study, the property of diesel engine was described as composed of combustion element including dead time and rotating element, and the ultimate gain for the speed control system to be located on the condition of stability limit was proposed based on the frequency characteristics. And the target gains with optimized stability also were proposed by giving proper margin to these ultimate conditions. The results were applied to a model system and the availability was confirmed to be satisfactory.

• Journal of Biosystems Engineering
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• 제12권3호
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• pp.42-49
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• 1987

The threshing action of the head-fed type threshing unit occurs mainly by the impact between threshing tooth and grains. It may be therefore the most fundamental step to calculate the time and order of the occurrance of impact by the tooth for predicting the performance of threshing unit. The threshing teeth arrangement was defined by length and diameter of threshing dram, number of spiral arrays, number of threshing teeth by kind per one spiral array, number of windings of spiral array around the threshing drum, delay angle of impact line. The linear equations for locus of left and right margin of paddy bundle, spiral array, impact line on the development figure of the threshing drum were expressed by fastors of the threshing teeth arrangement. In the computer program, the teeth which inflict impact were searched successively along the impact line. Searching range and impact condition were defined by the relation between four linear equations. If the impacting tooth was found, time and the kind of threshing tooth was derived from the coordinate of the threshing tooth. At this time the unit torque curve was accumulated on the array of computer memory. At last the completed torque curve of threshing drum shaft was described on the computer screen. Remarkably the peack valae and fluctuation of torque curve was decreased by adopting the delay angle of impact line.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제4권5호
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• pp.691-708
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• 2010

An important issue of supporting multi-users with diverse quality-of-service (QoS) requirements over wireless networks is how to optimize the systematic scheduling by intelligently utilizing the available network resource while, at the same time, to meet each communication service QoS requirement. In this work, we study the problem of a variety of communication services over multi-media heterogeneous cognitive OFDM system. We first divide the communication services into two parts. Multimedia applications such as broadband voice transmission and real-time video streaming are very delay-sensitive (DS) and need guaranteed throughput. On the other side, services like file transmission and email service are relatively delay tolerant (DT) so varying-rate transmission is acceptable. Then, we formulate the scheduling as a convex optimization problem, and propose low complexity distributed solutions by jointly considering channel assignment, bit allocation, and power allocation. Unlike prior works that do not care computational complexity. Furthermore, we propose the FAASA (Fairness Assured Adaptive Sub-carrier Allocation) algorithm for both DS and DT users, which is a dynamic sub-carrier allocation algorithm in order to maximize throughput while taking into account fairness. We provide extensive simulation results which demonstrate the effectiveness of our proposed schemes.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권8호
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• pp.407-414
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• 2004

In this paper, a new gray scale expression method that divides the scan lines into multiple blocks is suggested. The proposed method can drive 16 sub-fields per 1 TV field in the panel with XGA ($1366{\times}768$) resolution. The on and off states of even subfields depend on the condition of odd subfields. The write address mode is used in the odd subfields, while the erase address mode is used in the even subfields. Because the ramp reset pulse is applied every 2 sub-fields, both the contrast ratio and the dynamic voltage margin are sufficiently obtained in comparison with previous AWD (Address While Display) methods. In realizing 16 subfields, shortening the scan time in the erase address period was important. The X bias voltage in the erase address period affected the minimum address voltage but did not the delay time of the address discharge. The delay time of the address discharge was affected by the address voltage and the time interval between the last sustain discharge and the scanning time. We also evaluated the dynamic false contour. New method shows an improved image quality in horizontal moving, but discontinuous lines were observed at the boundaries of each block in vertical moving

• Restorative Dentistry and Endodontics
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• 제26권4호
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• pp.263-272
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• 2001

저광도 중합법, 펄스 지연 중합법, 초고광도 중합법 등의 광조사 방식이 광중합형 복합레진 수복물에서의 중합수축 응력에 미치는 영향을 알아보기 위해 in vitro에서 미세 누출 실험을 하였다. 80개의 발거된 소구치의 협측면에 5급 와동을 형성하고, 600mW/$cm^2$로 30초간 광조사하는 보통 광도 중합군, 300mW/$cm^2$로 60초간 광조사하는 저광도 중합군, 400mW/$cm^2$로 2초간 광조사하고 5분간 기다린 후 800mW/$cm^2$로 10초간 최종 중합시키는 펄스-지연 중합군, 그리고 1930mW/$cm^2$의 광도로 3초간 광조사하는 초고광도 중합군 등의 4개의 군으로 나누어 hybrid 형의 광중합복합레진을 충전하고 각 군의 방법대로 중합한 후, 변연의 0.5mm 외부에 nail varnish를 도포하고 37$^{\circ}C$, 2% metylene blue 용액에 24시간 동안 침적시켰다. 시편을 아크릴릭 레진에 매몰한 후 수복물의 중앙에서 종절단하여 입체현미경하에서 그 단면을 관찰한 후 법랑질과 상아질 변연으로 나누어 색소의 침투도를 측정하여 다음과 같은 결과를 얻었다. 1. 펄스 지연 중합군의 색소 침투도는 법랑질과 상아질 변연 모두에서 보통광도, 저광도 및 초고광도 중합군과 유의한 차이를 보이지 않았다(p>0.05). 2. 상아질 변연에서 초고광도 중합군은 보통광도 중합군과 저광도 중합군에 비해 유의하게 높은 색소 침투도를 보였다(p<0.05). 3. 법랑질 변연에서의 4개 군의 색소 침투도는 서로 유의한 차이를 보이지 않았다(p>0.05). 4. 모든 군에서 상아질 변연에서의 색소 침투도는 법랑질군에서의 색소 침투도에 비해 유의하게 높았다(p<0.05).

• 전자공학회논문지
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• 제50권8호
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• pp.136-142
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• 2013

DDR4와 같은 고속동작을 위한 메모리 제품에서, 데이타의 신뢰도 증가를 위해 CRC 기능이 추가되었다. 기존의 CRC 방식은 많은 부가회로 면적과 지연시간이 요구되기 때문에 고속동작의 메모리 제품에서 CRC 계산을 위한 내부 타이밍 마진의 부족현상이 증가한다. 따라서 본 논문에서는 이러한 문제를 해결할 수 있도록 matrix형 CRC 방법을 제시하고 CRC 계산을 빠르게 할 수 있는 XOR/XNOR 게이트를 제시하였다. matrix형 CRC는 모든 홀수 비트오류를 검출 가능하며, 4의 배수비트 오류를 제외한 짝수비트오류도 검출가능하다. 또한 단일오류(single error)에 대해서는 오류 정정이 가능하여 메모리 제품과 시스템간의 CRC 오류로 인한 데이터 재 전송의 부하를 감소시킬 수 있다. 또한 기존 방식대비 부가회로면적을 57% 개선할 수 있다. 제안한 XOR/XNOR는 6개의 TR.(트랜지스터)로 구성하였으며, 기존의 CRC 대비 35%의 면적 오버헤드를 감소시킬 수 있으며, 50%의 게이트 지연을 감소시킬 수 있다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.1864-1866
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• 1997

Uncertainties in the aerodynamic coefficients or time delay effects in implementing an autopilot algorithm can make a Flight Control System(FCS) unstable. When a FCS enters unstable state, the actuator or sensor limiters in FCS make the unstable system not diverge but be in the state of stable limit cycle. If an autopilot recognize the FCS to be in the stable limit cycle phenomenon, it woudl be better to adjust autopilot gains to stabilize the FCS. A novel method to stabilize a FCS using parameter estimation and maintenance of given phase margin is proposed. The method is applied to roll control loop and verified its performance.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1391-1394
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• 2007

In this work, the discharge characteristics and temporal distribution of surface charges on the Sidoped MgO have been investigated and elucidated with the results of photon-induced surface current. Even though the Si doped MgO shows lower static voltage margin, higher luminous efficacy, and shorter statistical delay time, its discharge characteristics become deteriorated as the timing of scanning is delayed from the ramp type reset pulse down. Overall features of Si-doped MgO in discharge characteristics are well correlated with surface current characteristics.

• 대한전자공학회논문지
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• 제26권10호
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.