• Title/Summary/Keyword: Delay Margin

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A Study On the Gain Setting of a Digital Governor for Marine Diesel Engines by Dynamic Calculation (선박 주기관 디지털 거버너의 동적 이득 설정에 관한 연구)

  • 강인철;최순만;최재성
    • Journal of Advanced Marine Engineering and Technology
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    • v.26 no.5
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    • pp.565-572
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    • 2002
  • The design concept of diesel engines for sea-going ships has been directed to Low-speed/Long-Stroke type to improve the efficiencies of combustion and propelling. But time-delay inevitable at low speed gives much difficulties for governors to control the engine speed because they would be apt to go into unstable region especially when operating at low speed. The purpose of this paper is to study the problem of how the governor gain can be calculated dynamically in accordance with the valiance of engine speed to locate the engine still on the properly stable condition. In this study, the property of diesel engine was described as composed of combustion element including dead time and rotating element, and the ultimate gain for the speed control system to be located on the condition of stability limit was proposed based on the frequency characteristics. And the target gains with optimized stability also were proposed by giving proper margin to these ultimate conditions. The results were applied to a model system and the availability was confirmed to be satisfactory.

Optimizing the design factors of the head-fed type combine(I) -Estimation of the threshing drum torque curve- (자탈형 콤바인 탈곡부 설계요인(設計要因)의 적정화(適正化)를 위한 연구(I) -급동축(扱胴軸) 토오크 파형의 추정(推定)-)

  • Nam, S.I.;Chung, C.J.;Hosokawa, A.
    • Journal of Biosystems Engineering
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    • v.12 no.3
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    • pp.42-49
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    • 1987
  • The threshing action of the head-fed type threshing unit occurs mainly by the impact between threshing tooth and grains. It may be therefore the most fundamental step to calculate the time and order of the occurrance of impact by the tooth for predicting the performance of threshing unit. The threshing teeth arrangement was defined by length and diameter of threshing dram, number of spiral arrays, number of threshing teeth by kind per one spiral array, number of windings of spiral array around the threshing drum, delay angle of impact line. The linear equations for locus of left and right margin of paddy bundle, spiral array, impact line on the development figure of the threshing drum were expressed by fastors of the threshing teeth arrangement. In the computer program, the teeth which inflict impact were searched successively along the impact line. Searching range and impact condition were defined by the relation between four linear equations. If the impacting tooth was found, time and the kind of threshing tooth was derived from the coordinate of the threshing tooth. At this time the unit torque curve was accumulated on the array of computer memory. At last the completed torque curve of threshing drum shaft was described on the computer screen. Remarkably the peack valae and fluctuation of torque curve was decreased by adopting the delay angle of impact line.

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A Novel Resource Allocation Algorithm in Multi-media Heterogeneous Cognitive OFDM System

  • Sun, Dawei;Zheng, Baoyu
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.4 no.5
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    • pp.691-708
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    • 2010
  • An important issue of supporting multi-users with diverse quality-of-service (QoS) requirements over wireless networks is how to optimize the systematic scheduling by intelligently utilizing the available network resource while, at the same time, to meet each communication service QoS requirement. In this work, we study the problem of a variety of communication services over multi-media heterogeneous cognitive OFDM system. We first divide the communication services into two parts. Multimedia applications such as broadband voice transmission and real-time video streaming are very delay-sensitive (DS) and need guaranteed throughput. On the other side, services like file transmission and email service are relatively delay tolerant (DT) so varying-rate transmission is acceptable. Then, we formulate the scheduling as a convex optimization problem, and propose low complexity distributed solutions by jointly considering channel assignment, bit allocation, and power allocation. Unlike prior works that do not care computational complexity. Furthermore, we propose the FAASA (Fairness Assured Adaptive Sub-carrier Allocation) algorithm for both DS and DT users, which is a dynamic sub-carrier allocation algorithm in order to maximize throughput while taking into account fairness. We provide extensive simulation results which demonstrate the effectiveness of our proposed schemes.

A New Driving Method for Gray-scale Expression in an AC Plasma Display Panel (교류형 플라즈마 디스플레이 패널에서 계조표현을 위한 새로운 구동방식)

  • 김재성;황현태;서정현;이석현
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.53 no.8
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    • pp.407-414
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    • 2004
  • In this paper, a new gray scale expression method that divides the scan lines into multiple blocks is suggested. The proposed method can drive 16 sub-fields per 1 TV field in the panel with XGA ($1366{\times}768$) resolution. The on and off states of even subfields depend on the condition of odd subfields. The write address mode is used in the odd subfields, while the erase address mode is used in the even subfields. Because the ramp reset pulse is applied every 2 sub-fields, both the contrast ratio and the dynamic voltage margin are sufficiently obtained in comparison with previous AWD (Address While Display) methods. In realizing 16 subfields, shortening the scan time in the erase address period was important. The X bias voltage in the erase address period affected the minimum address voltage but did not the delay time of the address discharge. The delay time of the address discharge was affected by the address voltage and the time interval between the last sustain discharge and the scanning time. We also evaluated the dynamic false contour. New method shows an improved image quality in horizontal moving, but discontinuous lines were observed at the boundaries of each block in vertical moving

EFFECT OF LIGHT IRRADIATION MODES ON THE MARGINAL LEAKAGE OF COMPOSITE RESIN RESTORATION (광조사 방식이 복합레진 수복물의 변연누출에 미치는 영향)

  • 박은숙;김기옥;김성교
    • Restorative Dentistry and Endodontics
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    • v.26 no.4
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    • pp.263-272
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    • 2001
  • The aim of this study was to investigate the influence of four different light curing modes on the marginal leakage of Class V composite resin restoration. Eighty extracted human premolars were used. Wedge-shaped class Y cavities were prepared on the buccal surface of the tooth with high-speed diamond bur without bevel. The cavities were positioned half of the cavity above and half beyond the cemento-enamel junction. The depth, height, and width of the cavity were 2 mm, 3 mm and 2 mm respectively. The specimens were divided into 4 groups of 20 teeth each. All the specimen cavities were treated with Prime & Bond$^{R}$ NT dental adhesive system (Dentsply DeTrey GmbH, Germany) according to the manufacturer's instructions and cured for 10 seconds except group VI which were cured for 3 seconds. All the cavities were restored with resin composite Spectrum$^{TM}$ TPH A2 (Dentsply DeTrey GmbH, Germany) in a bulk. Resin composites were light-cured under 4 different modes. A regular intensity group (600 mW/${cm}^2$, group I) was irradiated for 30 s, a low intensity group (300 mW/${cm}^2$, group II) for 60 s and a ultra-high intensity group (1930 mW/${cm}^2$, group IV) for 3 s. A pulse-delay group (group III) was irradiated with 400 mW/${cm}^2$ for 2 s followed by 800 mW/${cm}^2$ for 10 s after 5 minutes delay. The Spectrum$^{TM}$ 800 (Dentsply DeTrey GmbH, Germany) light-curing units were used for groups I, II and III and Apollo 95E (DMD, U.S.A.) was used for group IV. The composite resin specimens were finished and polished immediately after light curing except group III which were finished and polished during delaying time. Specimens were stored in a physiologic saline solution at 37$^{\circ}C$ for 24 hours. After thermocycling (500$\times$, 5-55$^{\circ}C$), all teeth were covered with nail varnish up to 0.5 mm from the margins of the restorations, immersed in 37$^{\circ}C$, 2% methylene blue solution for 24 hours, and rinsed with tap water for 24 hours. After embedding in clear resin, the specimens were sectioned with a water-cooled diamond saw (Isomet$^{TM}$, Buehler Co., Lake Bluff, IL, U.S.A.) along the longitudinal axis of the tooth so as to pass the center of the restorations. The cut surfaces were examined under a stereomicroscope (SZ-PT Olympus, Japan) at ${\times}$25 magnification, and the images were captured with a CCD camera (GP-KR222, Panasonic, Japan) and stored in a computer with Studio Grabber program. Dye penetration depth at the restoration/dentin and the restoration/enamel interfaces was measured as a rate of the entire depth of the restoration using a software (Scion image, Scion Corp., U.S.A.) The data were analysed statistically using One-way ANOVA and Tukey's method. The results were as follows : 1. Pulse-Delay group did not show any significant difference in dye penetration rate from other groups at enamel and dentin margins (p>0.05) 2. At dentin margin, ultra-high intensity group showed significantly higher dye penetration rate than both regular intensity group and low intensity group (p<0.05). 3. At enamel margin, there were no statistically significant difference among four groups (p>0.05). 4. Dentin margin showed significantly higher dye penetration rate than enamel margin in all groups (p<0.05).

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Matrix type CRC and XOR/XNOR for high-speed operation in DDR4 and GDDR5 (DDR4/GDDR5에서 고속동작을 위한 matrix형 CRC 및 XOR/XNOR)

  • Lee, JoongHo
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.136-142
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    • 2013
  • CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.

Autopilot gain adjustment for flight control system with limiter (제한기가 있는 비행제어시스템의 자동조종 알고리듬 이득 조정)

  • 최동균;유재종;김종환
    • 제어로봇시스템학회:학술대회논문집
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    • 1997.10a
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    • pp.1864-1866
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    • 1997
  • Uncertainties in the aerodynamic coefficients or time delay effects in implementing an autopilot algorithm can make a Flight Control System(FCS) unstable. When a FCS enters unstable state, the actuator or sensor limiters in FCS make the unstable system not diverge but be in the state of stable limit cycle. If an autopilot recognize the FCS to be in the stable limit cycle phenomenon, it woudl be better to adjust autopilot gains to stabilize the FCS. A novel method to stabilize a FCS using parameter estimation and maintenance of given phase margin is proposed. The method is applied to roll control loop and verified its performance.

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The Digital Controller of the Single-Phas Power Factor Correction(PFC) having the Variable Gain (가변 이득을 가지는 단상 PFC 디지털 제어기)

  • 정창용
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.163-167
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    • 2000
  • This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

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Characteristics of Si impurity doped MgO in an ac PDP

  • Ha, Chang-Hoon;Kim, Joong-Kyun;Whang, Ki-Woong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08b
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    • pp.1391-1394
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    • 2007
  • In this work, the discharge characteristics and temporal distribution of surface charges on the Sidoped MgO have been investigated and elucidated with the results of photon-induced surface current. Even though the Si doped MgO shows lower static voltage margin, higher luminous efficacy, and shorter statistical delay time, its discharge characteristics become deteriorated as the timing of scanning is delayed from the ramp type reset pulse down. Overall features of Si-doped MgO in discharge characteristics are well correlated with surface current characteristics.

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Design of MYNAMIC CMOS ARRAY LOGIC (DYNAMIC CMOS ARRAY LOGIC의 설계)

  • 한석붕;임인칠
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.10
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    • pp.1606-1616
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    • 1989
  • In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

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