• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.108-116
• /
• 2013

The input buffer in Network on Chip (NoC) router plays a key role in on-chip-network performance, which is utilized in flow control and virtual channel. However, increase in area and power due to input buffers as the network size gets larger is becoming severe. To solve this problem, a bufferless deflection routing without input buffer was suggested. Since the bufferless deflection routing shows poor performance at high network load, other approaches which combine the deflection routing with small size side buffers were also proposed. Nonetheless these new methods still show deficiencies caused by frequent path collisions. In this paper, we propose a modified deflection routing technique using a location based priority. In comparison with existing deflection routers, experimental results show improvement by 12% in throughput with only 3% increase in area.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2004.10a
• /
• pp.902-907
• /
• 2004

In this paper, a multi-step optimization using a G.A. (Genetic Algorithm) with variable penalty function is introduced to the structural design optimization of a 5-head route machine. Our design procedure consist of two design optimization stage. The first stage of the design optimization is static design optimization. The following stage is dynamic design optimization stage. In the static optimization stage, the static compliance and weight of the structure are minimized simultaneously under some dimensional constraints and deflection limits. On the other hand, the dynamic compliance and the weight of the machine structure are minimized simultaneously in the dynamic design optimization stage. As the results, dynamic compliance of the 5-head router machine was decreased by about 37％ and the weight of the structure was decreased by 4.48％ respectively compared with the simplified structure model.