• Journal of KIISE:Software and Applications
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• v.33 no.10
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• pp.823-835
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• 2006

Multimedia is a very popular service in the Internet. But, we cannot provide multimedia service at a uniform content, because networks and devices are various. Thus, an adaptive service is needed for multimedia transmission. Video Transcoding is the good solution that can service multimedia adaptively. This paper proposes the streaming system that is composed of encoder, transcoder, decoder The encoder enhanced time complexity and PSNR in case of transcoding using PP(Prediction Period). The decoder is almost same as the traditional media player. Transcoder reduced time complexity through combination of prediction period in encoder and skipping period to control frame rate in transcoder. In simulation results, the performances of proposed scheme outperform the system with traditional transcoder in time complexity and PSNR.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.551-558
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• 2008

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.53-64
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• 2011

In this paper, we propose a channel estimation of side information method based received motion vectors for distributed video coding. The proposed decoder estimates motion vectors of side information and transmits it to the encoder. As the proposed encoder generates side information which is the same to one in the decoder with received motion vectors, accuracy of side information of the decoder is assessed and it is transmitted to decoder. The proposed decoder can also estimate accurate crossover probability with received error information. As the proposed method conducts correct belief propagation, computational complexity of the channel decoder decreases and error correction capability is significantly improved with the smaller amount of parity bits. Experimental results show that the proposed algorithm is better in rate-distortion performance and it is faster than several conventional distributed video coding methods.

• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.3
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• pp.7-14
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• 2003

MPEG-1 audio standard is the algorithm for the compression of high-qualify digital audio signals. The standard dictates the functions of encoder and decoder pair, and includes three different layers as the complexity and the performance of the encoder and decoder. In this paper, we implemented the real-time system of MPEG-1 audio layer III decoder(MP3) with the TMS320C541 fixed point DSP chip. MP3 algorithm uses psycho-acoustic characteristic of human hearing system, and it reduces the amount of data with eliminating the signals hard to be heard to the hearing system of human being. It is difficult to implement MP3 decoder with fixed Point DSP because of it's broad dynamic range. We implemented realtime system with fixed DSP chip by using weighted look-up tables to reduce the amount of calculation and solve the problem of broad dynamic range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.459-470
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• 2008

In this paper, we propose a fast ME (motion estimation) algorithm for MPEG-4 to H.264 Transcoder. Whereas 2 modes ($8{\times}8$, $16{\times}16$) are used for ME in MPEG-4 simple profile, ME using 7 modes is supported for further enhanced coding efficiency in H.264. The transcoding speed is affected dominantly by the computational complexity of encoder part in transcoder, where ME module of H.264 encoder has high complexity due to using 7 modes. In order to increase the speed of transcoding between MPEG-4 and H.264, we use 3 PMVs (predicted motion vectors) and the mode information of MBs (macroblocks) provided from the decoder part of transcoder. Since the proposed 3 PMVs are very close to an optimal motion vector, and we consider only some restricted modes according to the MB information transferred from decoder part, the proposed scheme can speed up the transcoding procedure without loss of image quality. We show experimental results which demonstrate the effectiveness of the proposed algorithm, where performance of our scheme is compared with that of the conventional fast algorithm for H.264.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.185-192
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• 1999

In this paper. for $\pi$/4 and $\pi$/8 PSK. we proposed to condition to obtain coding gain increasing states, by design encoder of analytical method with minimal complexity in limited bandwidth and power channels. In order to improve the bit error rate(BER), comparing Ungerboeck designed the TCM. we propose MTCM(Multiple trellis-coded modulation) with multiplicity(k＝2), by optimum encoder design. By design encoder of analytical method. the trellis encoder can be minimal complexity and the decoder be used Viterbi decoder(MLSE). When compared to the TCM and MTCM with AWGN channels. the condition of performance enhancement of the MTCM with multiplicity(k＝2) is the case of parallel transition in TCM systems. without alternating data transmission rate in bandwidth and power limited channels.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.3
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• pp.125-131
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• 2002

In this paper, a new concatenation scheme of serial concatenated convolutional codes is proposed and the performance analyzed. In the proposed scheme, each of information and parity bits of outer code is entered into inner code through interleaver and deinterleaver. Therefore, the interleaver size is same as the length of input frame. Since the interleaver size of proposed type is reduced to half of the conventional Benedetto type, the interleaver delay time required for iterative decoding is reduced. In addition the multiplexer and demultiplexer are not used in the decoder of the proposed type, the complexity of decoder can be also reduced. As results of simulation, the performance of proposed type shows the better error performance as compared to that of the conventional Benedetto type in case of the same interleaver size. And it can be observed that the difference of BER performance is increased with the increase of Eb/No. In case of the same length of input frame, the proposed type shows almost same performance with Benedetto type despite that the interleaver size is reduced by half.