• Smart Structures and Systems
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• v.31 no.4
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• pp.351-363
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• 2023

Visual structural inspections are an inseparable part of post-earthquake damage assessments. With unmanned aerial vehicles (UAVs) establishing a new frontier in visual inspections, there are major computational challenges in processing the collected massive amounts of high-resolution visual data. We propose twin deep learning models that can provide accurate high-resolution structural components and damage segmentation masks efficiently. The traditional approach to cope with high memory computational demands is to either uniformly downsample the raw images at the price of losing fine local details or cropping smaller parts of the images leading to a loss of global contextual information. Therefore, our twin models comprising Trainable Resizing for high-resolution Segmentation Network (TRS-Net) and DmgFormer approaches the global and local semantics from different perspectives. TRS-Net is a compound, high-resolution segmentation architecture equipped with learnable downsampler and upsampler modules to minimize information loss for optimal performance and efficiency. DmgFormer utilizes a transformer backbone and a convolutional decoder head with skip connections on a grid of crops aiming for high precision learning without downsizing. An augmented inference technique is used to boost performance further and reduce the possible loss of context due to grid cropping. Comprehensive experiments have been performed on the 3D physics-based graphics models (PBGMs) synthetic environments in the QuakeCity dataset. The proposed framework is evaluated using several metrics on three segmentation tasks: component type, component damage state, and global damage (crack, rebar, spalling). The models were developed as part of the 2^nd International Competition for Structural Health Monitoring.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.11-20
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• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.