• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.993-1000
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• 2012

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an "as-early-as-possible" basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is $N{\times}N$ and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is $N^2(1-2^{-2J})/3$.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.1
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• pp.59-68
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• 2000

This paper proposes efficient VLSI architectures for computation of the 2- D discrete wavelet transform (DWT). The two proposed VLSI architectures for the 2- D DWT are constructed based on block-based computation Each $M{\times}N$ ($N{\times}M$) block DWT is performed along the row (column) direction simultaneously, where M and N denote the number of filter taps and the number of columns (rows), respectively The proposed architectures compute the lowpass and highpass output sequences of the 1 - DWT along the row and column directions using a single architecture In alternate clock cycles Therefore the extra processing units required for the proposed architectures are much smaller than those of the conventional architectures They are modeled In very high speed Integrated circuit hardware description language (HIDL) and Simulated to show their functional validity.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.6
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• pp.1343-1352
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• 2018

This paper is designed for hardware to be applied to JPEG2000 standard in the fields of digital photography, remote sensing, aerial remote telemetry, medical imaging, high resolution, and high compression telemetry applications. The software implementation of the JPEG2000 standard for image compression has disadvantages that the processing speed is very slow compared to the conventional JPEG, also the degradation occurs when the DWT level of the JPEG2000 standard is improved. In order to solve this problem, we designed and applied JPEG2000 compression/decompressor. In this paper, the hardware of the JPEG 2000 compression/storage device shows optimal compression speed, faster processing speed, and the image quality for still images by changing the optimal DWT level.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.7 no.2
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• pp.143-147
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• 2007

This paper proposes a new watermarking scheme in which a logo watermark is embedded into the discrete wavelet transform (DWT) domain of the original image using exact radial basis function neural networks (RBF). RBF will learn the characteristics of the image, and then watermark is embedded and extracted by the trained RBF. A watermark is added to the coefficients at the low frequency band of the DWT of an image and a watermark is embedded into the DWT domain using the trained RBF. The trained RBF also used in watermark extracting process. Experimental results show that the proposed method has good imperceptibility and high robustness to common image processing attacks.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1157-1160
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• 1998

This paper describes the design of a block data flow architecture(BDFA) which implements 2-D discrete wavelet transform(DWT)/inverse discrete wavelet transform(IDWT) for real time image processing applications. The BDFA uses 2-D product separable filters for DWT/IDWT. It consists of an input module, a processor array, and an output module. It use both data partitioning and algorithm partitioning to achieve high efficiency and high throughput. The 2-D DWT/IDWT algorithm for 256$\times$256 lenna image has been simulated using IDL(Interactive Data Language). The 2-D array structured BDFA for the 2-D filter has been modeled and simulated using VHDL.

• Proceedings of the Korea Multimedia Society Conference
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• 2012.05a
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• pp.340-342
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• 2012

Integral Imaging (II) is an attractive technique for three-dimensional (3D) image, video display and recording. Inherently, the high resolution II requires an enormous amount of data for storing and transmitting of 3D scenes. Compression techniques attempt to evade this issue. In this study, we made a comparative performance analysis of popular transforming/compression techniques such as the Discrete Cosine Transform (DCT) and the Discrete Wavelet Transform (DWT) in order to compress 3D-II. The standard baseline JPEG (Joint Photographic Experts Group) using DCT and JPEG 2000 using DWT methods were manipulated in our experiments. In our analysis, we have shown that the DWT based JPEG 2000 compression methodology could be a good alternative for 3D-II.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.10
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• pp.132-140
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• 1997

This paper proposes systolic array architectures for compuataion of the 1-D and 2-D discrete wavelet transform (DWT). The proposed systolic array for compuataion of the 1-D DWT consists of L processing element (PE) arrays, where the PE array denotes the systolic array for computation of the one level DWT. The proposed PE array computes only the product terms that are required for further computation and the outputs of low and high frequency filters are computed in alternate clock cycles. Therefore, the proposed architecuter can compute the low and high frequency outputs using a single architecture. The proposed systolic array for computation of the 2-D DWT consists of two systolic array architectures for comutation of the 1-D DWT and memory unit. The required time and hardware cost of the proposed systolic arrays are comparable to those of the conventional architectures. However, the conventional architectures need extra processing units whereas the proposed architectures fo not. The proposed architectures can be applied to subband decomposition by simply changing the filter coefficients.

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.311-315
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• 2004

In this paper, we proposed a robust watermarking algorithm based on fuzzy inference and human visual system. In the first, discrete wavelet transform(DWT) is involved to calculate additive energy strength, then we devised fuzzy inference, which was established by computing contrast and texture degree in gray-level image. Watermark is embeded into the coefficients of 3-level DWT so as to consider a spatial effects. Visual recognizable patterns such as binary image were used as a watermark Consequently, experimental results showed that proposed algorithm is robust in JPEC compression.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.3
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• pp.103-109
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• 2014

This study derived the inter-conversion matrices, which can be used in heterogeneous image transcoding between the compressed images using different transforms, such as the $8{\times}8$ block discrete cosine transform (BDCT) and the one-level discrete wavelet transform (DWT). Basically, to obtain the one-level DWT coefficients from $8{\times}8$ BDCT, inverse BDCT should be performed followed by forward DWT, and vice versa. On the other hand, if the proposed interconversion approach is used, only one inter-conversion matrix multiplication makes the corresponding transcoding possible. Both theoretical and experimental analyses showed that the amount of computation of the proposed approach decreases over 20% when the inter-conversion matrices are used under specific conditions.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.365-366
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• 2007

본 워터마크를 삽입 할 수 있는 임베디드 시스템을 구현 하였다. 워터마크 삽입을 위해 DWT와 Data Matrix가 사용되었다. DWT(Discrete Wavelet Transform)는 주파수 공간에서 워터마크를 삽입하기 위해 사용되었고, Data Matrix는 워터마크로 사용되었다. 데이터 매트릭스는 미국의 Data Matrix사가 만든 이차원 바코드로 오류검출 및 복원 알고리즘을 가지고 있어 작은 에러는 복원이 가능하다. 시스템으로는 PDA를 사용하였고, 틀로는 EVC를 사용하였다. 삽입 알고리즘은 다음과 같다. DWT를 한 경우 4개의 서브밴드로 나누어지며, 그 중 cV(horizontal detail)와 cH(vertical detail)를 선택하여 4*4블록 단위로 나눈다. 나누어진 블록과 대응하는 워터마크의 픽셀 값에 의해 계수에 일정 값(가중치)을 더하거나 때주어 워터마크를 삽입한다. 추출 알고리즘은 역으로 이루어진다. 성능평가는 PDA에서 워터마크 삽입 알고리즘을 통하여 워터마크를 삽입, 추출된 영상을 가지고 Matlap을 이용하여 평가하였다.