• Title/Summary/Keyword: DVB-S2 Systems

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Performance and Operating Characteristics Analysis of the 16-APSK Modulation over Nonlinear Channels (16-APSK 변조 방식의 성능 및 비선형 채널에서의 동작 특성 분석)

  • Kang, Seok-Heon;Kim, Sang-Tae;Sung, Won-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.4C
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    • pp.362-369
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    • 2007
  • APSK (Amplitude Phase Shift Keying) digital modulation is characterized by the circular positioning of the transmission symbols in the constellation diagram. Due to such structural characteristics, the peak-to-average power ratio of the APSK modulation is lower than that of the QAM (Quadrature Amplitude Modulation), and the amount of performance degradation over nonlinear channels can be mitigated. The APSK modulation scheme has recently been adopted as satellite communication system standards including the DVB-S2 (Digital Video Broadcasting - Satellite, Version 2). In this paper, a BER (Bit Error Rate) upper bound approximation formula is derived using the channel model with the output power saturation characteristics, and its accuracy is demonstrated. Using the derived formula, the input power level that minimizes the BER is determined. The optimized performance based on the radii ratio of the 16APSK constellation and the channel saturation level is also presented.

A 8192-point pipelined FFT/IFFT processor using two-step convergent block floating-point scaling technique (2단계 수렴 블록 부동점 스케일링 기법을 이용한 8192점 파이프라인 FFT/IFFT 프로세서)

  • 이승기;양대성;신경욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.10C
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    • pp.963-972
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    • 2002
  • An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

Adaptive Coding and Modulation Scheme for Ka Band Space Communications

  • Lee, Jae-Yoon;Yoon, Dong-Weon;Lee, Woo-Ju
    • Journal of Astronomy and Space Sciences
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    • v.27 no.2
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    • pp.129-134
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    • 2010
  • Rain attenuation can cause a serious problem that an availability of space communication link on Ka band becomes low. To reduce the effect of rain attenuation on the error performance of space communications in Ka band, an adaptive coding and modulation (ACM) scheme is required. In this paper, to achieve a reliable telemetry data transmission, we propose an adaptive coding and modulation level using turbo code recommended by the consultative committee for space data systems (CCSDS) and various modulation methods (QPSK, 8PSK, 4+12 APSK, and 4+12+16 APSK) adopted in the digital video broadcasting-satellite2 (DVB-S2).

The introductory study for MIMO techniques over satellite systems

  • Kang, Yeon-Su;Kang, Kun-Suk;Ahn, Do-Seob
    • Journal of Satellite, Information and Communications
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    • v.2 no.2
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    • pp.80-84
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    • 2007
  • In this paper, the introductory study of the multi input multi output (MIMO) techniques for satellite communication systems is presented. Because of the advantage of wide coverage of satellite, it has been considered for broadcasting services and fill-in services. On the other hand, state of the art multi input multi output (MIMO) techniques such as space time code (STC) and spatial multiplexing (SM) makes the terrestrial system increase link performance and their coverage, and also increase the link throughput. For these regard, in order to satisfy the requirements of the next generation communications and coexists with terrestrial systems harmoniously, the studying about satellite MIMO techniques is necessary. In this paper, we introduce some system model and scenarios to apply MIMO technique to intermediate module repeater (IMR). The possibility of these techniques and technical requirements are also considered. Especially, Space time code is used to enhance IMRs coverage and increase the link performance, and space time multiplexing is utilized to multiplex satellite broadcasting signals with local broadcasting signal in IMR cell.

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Implementation of systematic LT codes using VHDL (VHDL을 이용한 시스터메틱 LT 부호의 구현)

  • Zhang, Meixiang;Kim, Sooyoung;Chang, Jin Yeong;Kim, Won-Yong
    • Journal of Satellite, Information and Communications
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    • v.9 no.2
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    • pp.45-51
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    • 2014
  • Luby transform (LT) codes are a class of ratelss codes, and they have capability of generating infinite length of parities with a given information length. These rateless codes can be effectively utilized to provide broadcasting and multicasting services where each user is in a different channel condition. For this reason, there have been a number of researches on the application of rateless codes for satellite systems. In this paper, by considering the current research status on rateless codes, we present VHLD implementation results of LT codes, for future hardware implementation for satellite systems. The results demonstrated in this paper can be utilized as a basic information on efficient utilization of rateless codes in the future satellite systems.

Complexity-Reduced Algorithms for LDPC Decoder for DVB-S2 Systems

  • Choi, Eun-A;Jung, Ji-Won;Kim, Nae-Soo;Oh, Deock-Gil
    • ETRI Journal
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    • v.27 no.5
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    • pp.639-642
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    • 2005
  • This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.

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Cooperative Diversity using Cyclic Delay for OFDM systems (OFDM 시스템을 위한 순환 지연을 사용하는 협력 다이버시티 기법)

  • Lee, Dong-Woo;Jung, Young-Seok;Lee, Jae-Hong
    • Journal of Broadcast Engineering
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    • v.13 no.2
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    • pp.172-178
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    • 2008
  • Orthogonal Frequency Division Multiplexing (OFDM) is one of the most promising technologies for high data rate wireless communications. OFDM has been adopted in wireless standards such as digital audio/video broadcasting. The combination of OFDM and cooperative diversity techniques can provide the diversity gain and/or increased capacity. In this paper, the cooperative coding using cyclic delay diversity (CDD) for multiuser OFDM systems is introduced. To improve the beneficial effects of relays's cooperation, CDD is adopted in cooperative transmission of relays. Simulation results show the bit error rate (BER) for various consideration. The proposed scheme provides improved performance compared to delay.

Wideband CMOS Voltage-Controlled Oscillator(VCO) for Multi-mode Vehicular Terminal (융복합 차량 수신기를 위한 광대역 전압제어 발진기)

  • Choi, Hyun-Seok;Diep, Bui Quag;Kang, So-Young;Jang, Joo-Young;Bang, Jai-Hoon;Oh, Inn-Yul;Park, Chul-Soon
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.7 no.6
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    • pp.63-69
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    • 2008
  • Reconfigurable RF one-chip solutions have been researched with the objective of designing for smaller-sized and more economical RF transceiver and it can be applied to a vehicular wireless terminal. The proposed voltage-controlled oscillator satisfies the targeted frequency range ($4.2{\sim}5.4\;GHz$) and the frequency planning which correspond to the standards such as CDMA(IS-95), PCS, GSM850, EGSM, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, and DVB-H/DMB-H/L(L Band). In order to improve phase noise performance, PMOS is adopted in the cross-coupled pair, the tail current source and MOS varactor in this VCO and differential-typed switching is proposed in capacitor array. Based on the measurement results, a total power dissipation is $5.3{\sim}6.0\;mW$ at 1.8 V power supply voltage. The oscillator is tuned from 4.05 to 5.62 GHz; The tuning range is 33%. The phase noise is -117.16 dBc/Hz at 1 MHz offset frequency and the FOM (Figure Of Merit) is $-180.84{\sim}-180.5$.

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Frame Synchronization Method for Distributed MIMO Terrestrial Broadcasting Systems (분산 다중 안테나 지상파 방송 시스템을 위한 프레임 동기화 방법)

  • Ok, Kyu-Soon;Kang, In-Woong;Kim, Youngmin;Seo, Jae Hyun;Kim, Heung Mook;Kim, Hyoung-Nam
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.4
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    • pp.424-432
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    • 2016
  • World's leading countries are developing next generation digital broadcasting system specifications to support UHDTV (ultra-high definition television) contents and other various services. In order to maximize the transmission capacity by using the bandwidth efficiently, most broadcasting systems adopt MIMO-OFDM. In distributed-MIMO systems, multiple transmit antennas are spatially separated and therefore result in multiple timing offsets. To overcome this problem, this paper proposes a technique using a null symbol to detect each individual signal from distributed transmit antennas. By inserting null symbols before preambles, the receiver can distinguish the signals between each transmit antennas and perform frame synchronization. When the reception time difference is shorter than 500 samples, the proposed method outperforms the conventional method.

A 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting applications (DMB 응용을 위한 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D 변환기)

  • Cho, Young-Jae;Kim, Yong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.37-47
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    • 2006
  • This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.