• Title/Summary/Keyword: DUT

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Analysis of biomarkers with tunable infrared gas sensors (가변 파장형 적외선 가스 센서에 의한 생체표지자 분석)

  • Yi, Seung Hwan
    • Journal of Sensor Science and Technology
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    • v.30 no.5
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    • pp.314-319
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    • 2021
  • In this study, biomarkers were analyzed and segmented using tunable infrared gas sensors after performing the principal component analysis. The free spectral range of the device under test (DUT) was around 30 nm and DUT-5580 yielded the highest output voltage property among the others. The biomarkers (isoprophyl alcohol, ethanol, methanol, and acetone solutions) were sequentially mixed with deionized water and their mists were carried into the gas chamber using high-purity nitrogen gas. A total of 17 different mixed gases were tested with three tunable infrared gas sensors, namely DUT-3144, DUT-5580, and DUT-8010. DUT-8010 resolved the infrared absorption spectra of whole mixed gases. Based on the principal component analysis with each DUT and their combinations, each mixed gas and the trends in increasing gas concentration could be well analyzed when the contributions of the eigenvalues of the first and second were higher than 70% and 10%, respectively, and their sum was greater than 90%.

Design of Optimal Thermal Structure for DUT Shell using Fluid Analysis (유동해석을 활용한 DUT Shell의 최적 방열구조 설계)

  • Jeong-Gu Lee;Byung-jin Jin;Yong-Hyeon Kim;Young-Chul Bae
    • The Journal of the Korea institute of electronic communication sciences
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    • v.18 no.4
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    • pp.641-648
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    • 2023
  • Recently, the rapid growth of artificial intelligence among the 4th industrial revolution has progressed based on the performance improvement of semiconductor, and circuit integration. According to transistors, which help operation of internal electronic devices and equipment that have been progressed to be more complicated and miniaturized, the control of heat generation and improvement of heat dissipation efficiency have emerged as new performance indicators. The DUT(Device Under Test) Shell is equipment which detects malfunction transistor by evaluating the durability of transistor through heat dissipation in a state where the power is cut off at an arbitrary heating point applying the rating current to inspect the transistor. Since the DUT shell can test more transistor at the same time according to the heat dissipation structure inside the equipment, the heat dissipation efficiency has a direct relationship with the malfunction transistor detection efficiency. Thus, in this paper, we propose various method for PCB configuration structure to optimize heat dissipation of DUT shell and we also propose various transformation and thermal analysis of optimal DUT shell using computational fluid dynamics.

Two Noise Parameter Measurement Methods Using Spectrum Analyzer and Comparison (스펙트럼 분석기를 이용한 2가지 잡음 파라미터 측정방법과 비교)

  • Lee, Dong-Hyun;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.12
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    • pp.1072-1082
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    • 2015
  • In this paper, we propose two noise parameter measurement methods using spectrum analyzer. First method, we measure a noise correlation matrix using the 6-port network, and we calculate noise parameters using measured a noise correlation matrix. Second method, we directly measure noise figures of the DUT for source impedance changes, and then noise parameters are extracted from the measured noise figures. In order to measure a noise figure, we present a method of measuring a noise figure of the DUT that have arbitrary source impedances using spectrum analyzer and a method of eliminating a noise effect of a impedance tuner. Finally, the noise parameters of a passive and active DUT using proposed two methods are compared. The comparison shows that the two results obtained from for the two methods give almost identical noise parameters. The noise parameters measured by 6-port network accurately predict measured noise figures of the DUT for source impedance changes, and noise parameters measured by 6-port network is verified from the comparison.

Measurement of Noise Wave Correlation Matrix for On-Wafer-Type DUT Using Noise Power Ratios (잡음전력비를 이용한 온-웨이퍼형 DUT의 잡음상관행렬 측정)

  • Lee, Dong-Hyun;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.30 no.2
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    • pp.111-123
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    • 2019
  • In this paper, we propose a method for defining the input termination for on-wafer-type device under test (DUT) measurement. Using the newly defined input termination and noise wave correlation matrix (NWCM) measurement method based on noise power ratio, the NWCM of the on-wafer-type DUT was measured. We demonstrate a noise measurement configuration that includes wafer probes and bias tees to measure the on-wafer DUT. The S-parameter of the adapter that combines the bias tee, probe, and a line terminated by open is required to define the input termination for on-wafer DUT measurement. To measure the S-parameter of the adapter, a 2-port S-parameter measurement method using 1-port measurement is introduced. Using the measured S-parameters, a method for defining the new input termination for on-wafer-type DUT measurement is applied. The proposed method involves the measurement of the NWCM of the chip with a 1.5 dB noise figure. The noise parameters of the chip were obtained using the measured NWCM. The results indicate that the obtained values of the noise parameters are similar to those mentioned on a datasheet for the chip. In addition, repeated measurements yielded similar results, thereby confirming the reliability of the measurements.

A Transactor Implementation for SoC Verification with iPROVE (iPROVE 기반 SoC 검증을 위한 트랜잭터 구현)

  • Cho, Chong-Hyun;Cho, Joong-Hwee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.4
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    • pp.73-79
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    • 2007
  • In this paper the proposed transactor is customized and a generator which roles of automatically generating the transactor according to DUT(Design Under Test)'s input and output is implemented. The customized transactor is designed by rearranging the signals of depending on DUT and transactor protocol which consists of signals of the PCI interface between host computer and FPGA(Field Programmable Gate Array). The implemented automatic generator of transactor generates a Verilog code of transactor by adding DUT's information about input and output ports. Performance and normal working of the generated transactor has been verified by experiments with some verified hardware IPs. Also, an efficiency of the transactor has been verified by comparing with user's manually designed transactor and generated transactor. Moreover, the generator's flexibility has been verified for DUT's information of variable input and output. In case of using the implemented generator, a design time of transactor is reduced.

Operation Charateristics of PHIL Simulator depending on DUT and PHIL Simulator Switching Frequency Ratio (DUT 및 PHIL 시뮬레이터 스위칭 주파수 비에 따른 PHIL 시뮬레이터 운전 특성)

  • Heo, Hong-Jun;Hwang, Seon-Woong;Jeong, Dong-Yeong;Kim, Jang-Mok
    • Proceedings of the KIPE Conference
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    • 2020.08a
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    • pp.245-247
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    • 2020
  • 본 논문에서는 DUT(Device Under Test) 및 PHIL(Power Hardware-in-the-Loop) 시뮬레이터의 스위칭 주파수 비 및 PWM 위상차에 의하여 발생할 수 있는 문제를 분석하였다. 또한, DUT 인버터의 PWM 특성을 고려한 디지털 필터를 적용하여 PHIL 시뮬레이터의 운전 영역을 확대하였다. 디지털 필터는 DUT 스위칭 주파수의 고조파 성분만을 선택적으로 제거하여 PHIL 스위칭 주파수에 무관하게 일정한 시뮬레이션 결과를 생성할 수 있다. 분석한 내용과 디지털 필터의 변경으로 인한 PHIL 시뮬레이터의 특성은 다양한 조건에서 시행된 실험을 통하여 검증하였다.

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Implementation of a Verification Environment using Layered Testbench (계층화된 테스트벤치를 이용한 검증 환경 구현)

  • Oh, Young-Jin;Song, Gi-Yong
    • Journal of the Institute of Convergence Signal Processing
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    • v.12 no.2
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    • pp.145-149
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    • 2011
  • Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

Measurement Method of Noise Correlation Matrix Using Relative Noise Ratio (상대적인 잡음비를 이용한 잡음상관행렬 측정방법)

  • Lee, Dong-Hyun;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.5
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    • pp.430-437
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    • 2016
  • In general, noise measurement results show larger random ripple than those of the network analyzer. The reason for the lager random ripple of the noise measurements is considered that the general noise measurements uses absolute measured noise powers, while the network analyzer measures using a ratio of the measured powers. In this paper, a novel measurement method of noise correlation matrix using relative noise ratios is proposed. Proposed method measures the five noise powers of DUT for the five input impedance variations and the four relative noise ratios are formed using the five measured noise powers. The four noise ratios are used to compute the noise correlation matrix and noise parameters. The resulting noise parameters for a 0.5 dB attenuator show good agreements with theoretical values calculated by S-parameters. Also, the noise parameters of an active DUT with a noise figure of less than 1 dB are measured and the measured results show a small random ripple as expected and their values are physically acceptable. In conclusion, the proposed method can be applied to the noise parameter measurements for DUT with a noise figure below 1 dB.

A SUPERLINEAR $\mathcal{VU}$ SPACE-DECOMPOSITION ALGORITHM FOR SEMI-INFINITE CONSTRAINED PROGRAMMING

  • Huang, Ming;Pang, Li-Ping;Lu, Yuan;Xia, Zun-Quan
    • Journal of applied mathematics & informatics
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    • v.30 no.5_6
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    • pp.759-772
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    • 2012
  • In this paper, semi-infinite constrained programming, a class of constrained nonsmooth optimization problems, are transformed into unconstrained nonsmooth convex programs under the help of exact penalty function. The unconstrained objective function which owns the primal-dual gradient structure has connection with $\mathcal{VU}$-space decomposition. Then a $\mathcal{VU}$-space decomposition method can be applied for solving this unconstrained programs. Finally, the superlinear convergence algorithm is proved under certain assumption.

AN APPROXIMATE ALTERNATING LINEARIZATION DECOMPOSITION METHOD

  • Li, Dan;Pang, Li-Ping;Xia, Zun-Quan
    • Journal of applied mathematics & informatics
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    • v.28 no.5_6
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    • pp.1249-1262
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    • 2010
  • An approximate alternating linearization decomposition method, for minimizing the sum of two convex functions with some separable structures, is presented in this paper. It can be viewed as an extension of the method with exact solutions proposed by Kiwiel, Rosa and Ruszczynski(1999). In this paper we use inexact optimal solutions instead of the exact ones that are not easily computed to construct the linear models and get the inexact solutions of both subproblems, and also we prove that the inexact optimal solution tends to proximal point, i.e., the inexact optimal solution tends to optimal solution.