• Title/Summary/Keyword: DTCP

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Design of a ECC arithmetic engine for Digital Transmission Contents Protection (DTCP) (컨텐츠 보호를 위한 DTCP용 타원곡선 암호(ECC) 연산기의 구현)

  • Kim Eui seek;Jeong Yong jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3C
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    • pp.176-184
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    • 2005
  • In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

Design of ECC Calculator for Digital Transmission Content Protection(DTCP) (디지털 컨텐츠 보호를 위한 DTCP용 타원곡선 암호(ECC) 연산기의 구현)

  • Kim Eui-Seok;Ryu Tae-Gyu;Jeong Yong-Jin
    • Proceedings of the IEEK Conference
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    • 2004.06a
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    • pp.47-50
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    • 2004
  • In this paper, we implement an Elliptic Curve Cryptosystem(ECC) processor for DTCP. Because DTCP(Digital Transmission Content Protection) uses GF(p), where p is a 160-bit prime integer, we design a scalar multiplier based on GF(p). The scalar multiplier consists of a modular multiplier and an adder. The multiplier uses montgomery algorithm which is implemented with CSA(Carry-save Adder) and CLA(Carry-lookahead Adder). Our new scalar multiplier has been synthesized using Samsung 0.18 um CMOS technology and the maximum operation frequency is estimated 98 MHz, with the size about 65,000 gates. The resulting performance is 29.6 kbps, that is, it takes 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

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TDX-1A의 디지틀 중계선 루프 신호처리 성능분석

  • An, Ji-Hwan;Park, Gwang-Ro;Lee, Yong-Gyun
    • ETRI Journal
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    • v.10 no.2
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    • pp.32-39
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    • 1988
  • In this paper, we describe an effective trunk loop signal processing method and anlayze execution time of the program in the DTCP (Digital Trunk Circuit Processor) in the TDX-1A digital switching stytem. And we also predict a maximum trunk capacity in the DTCP with respect to scanning period based on the call attempt characteristics which has the Poisson distribution.

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The Performance Analysis of The Digital Trunk Circuit Processor in The TDX-1A (TDX-1A의 디지틀 중계선 정합 프로세서의 성능분석)

  • Ahn, Jee-Hwan;Park, Kwang-Ro;Lee, Yong-Kyun
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.510-513
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    • 1988
  • This paper describes an effective trunk loop signal processing method and analyzes execution time of program in the DTCP(Digital Trunk Circuit Processor) in the TDX-1A digital switching system. To predict a maximum trunk capacity, also analyzes to Z80A system clock(4Mbit/s, 2.5Mbit/s) and scanning period(8mS,5mS) respectively.

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