• Journal of Power Electronics
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• 제11권2호
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• pp.113-119
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• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• The Journal of the Acoustical Society of Korea
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• 제19권4호
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• pp.45-51
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• 2000

This paper describes real-time implementation of a multi-channel G.729A speech coder using a 16 bit fixed-point Digital Signal Processor (DSP) and its application to a Voice Mailing Service (VMS) system. TMS320C549 by Texas Instruments was used as a fixed point DSP chip and a 4 channel G.729A coder was implemented on the chip. The implemented coder required 14.5 MIPS for the encoder and 3.6 MIPS for the decoder at each channel. In addition, memories required by the coder were 9.88K words and 1.69K words for code and data sections, respectively. As a result, the developed VMS system that accommodates two DSP chips was able to support totally 8 channels. Experimental results showed that the our multi-channel coder passes all of test vectors provided by ITU-T.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제35C권12호
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.

• Journal of IKEEE
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• 제26권2호
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• pp.280-286
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• 2022

This paper presents implementation of rapid control prototype (RCP) for permanent magnet synchronous machines (PMSMs) using a digital signal processor (DSP) and the PLECS software. By utilization of auto code generation function in the PLECS, a current vector control algorithm for a PMSM drive system using a DSP as a control processor can be developed more efficiently. In this paper, a background of a model based design (MBD) and real time control are reviewed. Also, commercial RCP products compatible with DSP boards are introduced. At the end of the paper, experimental implementation of RCP for a PMSM drive is presented.

• The Journal of the Korea Contents Association
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• 제8권5호
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• pp.72-81
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• 2008

High Performance DSP usually supports cache and internal memory. For an optimal implementation of a multimedia stream application on such a high performance DSP, one needs to utilize the cache and internal memory efficiently. In this paper, we investigate performance analysis of cache, and internal memory configuration and placement necessary to achieve an optimal implementation of multimedia stream applications like motion picture encoder on high performance DSP, TMS320C6000 series, and propose strategies to improve performance for cache and internal memory placement. From the results of analysis and experiments, it is verified that 2-way L2 cache configuration with the remaining memory configured as internal memory shows relatively good performance. Also, it is shown that L1P cache hit rate is enhanced when frequently called routines and routines having caller-callee relationships with them are continuously placed in the internal memory and that L1D cache hit rate is enhanced by the simple change of the data size. The results in the paper are expected to contribute to the optimal implementation of multimedia stream applications on high performance DSPs.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(4)
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• pp.187-190
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• 2000

In this paper, implementation of speech Recognizer system, Separated from Personal computer. By using DSP, this intends to extend the voice recognizing, limited into PC because of amount of data and calculations. For this performance The thesis uses the real time End point detector and organizes no additional device between human and the system, characteristic vector are that detects End point and voice from absolute energy and ZCR, that uses 12 difference Cepstrum from LPC, that uses the method to compensate the process of pattern separating and pre-calculated standard pattern limitation.

• Proceedings of the KIPE Conference
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• 전력전자학회 1996년도 창립기념 전력전자학술발표회 논문집
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• pp.93-98
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• 1996

This paper presents active silencer by hysteresis control method using DSP-scheme and shows it audible noise reduction effect. Pentium processor and sound blaster 16 are used for its implementation. The sound blaster 16 executes A/D, D/A conversion and is used operating source of loudspeaker for cancelling.

• The Journal of the Acoustical Society of Korea
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• 제14권1E호
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• pp.83-87
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• 1995

The implementation of the voice dodec is imjplemented by using TMS320C30, which is the floating point DSP chip from Texas Instrument. QCELP (Qualcomm Code Excited Linear Prediction) is used to encode and decode the voice. The QCELP code is implemented by the TMS320C30 C-dode. The DSP board is controlled by the PC. The PC program tranfors the voice file from and to the DSP board, which is also implemented by C-code. The voice is encoded by the DSP board and the encoded data is transferred to PC to be stored as a file. To hear the voice. the voice data file is sent to DSP board and decoded to synthesize audible voice. Two flags are used by both programs to notify the status of the operation. By checking the flags, DSP and PC decides when the voice data is transferred between them.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 1999년도 추계종합학술대회
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• pp.199-203
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• 1999

This paper is on the DSP system design and implementation for real time MPEG-2 AAC multichannel audio, and MPEG-4 object oriented audio coding. This DSP system employs two DSPs of the state of the art TMS320C6701, developed by TI semiconductor. DSP board has PCI interface for downloading application program and control the system. DSP board was designed to use for both encoder and decoder, by setting several switches. The system contains external input and output box also, for A/D and D/A conversion for eight channel audio. The input box converts multi channel digital audio to ADI format, that provides serial interface for eight channel digital audio. And the output box converts ADI format signal to multi channel audio. Through this ADI interface, DSP boards can be connected to input, output box. Implemented DSP system was tested for integration with MPEG-2 AAC encoder and decoder S/W. Currently the DSP system performs realtime AAC 4-channel audio encoding with two DSPs, and 8-channel decoding with one DSP.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제9권6호
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.