• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39C no.3
• /
• pp.275-281
• /
• 2014

Recently, the need for various underwater application systems targeting efficient resource exploration and aquatic ecosystem monitoring is rapidly increasing in littoral sea and inland waters. In this paper, we focus on the research and development of digital module of acoustic micro modem which can be used for underwater mobile communication systems and underwater sensor network systems. Specifically, a digital module of acoustic modem embedding digital signal processor is designed and implemented. On top of the developed hardware platform, physical layer frame generation and recovery and channel coding algorithms are mounted and tested in a water tank and a pond to verify its functionality and performance. According to experimental results, less than 1 percent of total computational power is consumed in the processing of frame control and convolutional code with the data rate of 1 kbps. Thus, the performance of micro modem could be improved by loading efficient baseband algorithms into the processor while maintaining the implemented hardware.

• Journal of IKEEE
• /
• v.22 no.3
• /
• pp.619-623
• /
• 2018

Due to the development of society, the demand for electric power has increased and the quality control of electric power has become an important issue. In order to efficiently perform such power management, we propose a DSP based power measurement system for multi-wire power measurement. Since the conventional power measurement system can measure only the power of one line, a power quality measurement device is required for each line in order to measure the power quality of the individual line. Respectively. The system proposed in this paper proposes a system capable of real-time measurement of power quality at up to 12 points using digital signal processing algorithm, and the prototype based on this system was evaluated through the official test report of Korea Electrotechnology Research Institute. As a result of the performance test, it was evaluated that the error range is excellent at ${\pm}0.3%$.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.16 no.4
• /
• pp.485-492
• /
• 2006

This paper deals with implementation of network for distributed control system of a humanoid robot ISHURO(Inha Semyung Humanoid Robot). A humanoid robot needs much degree of freedom structurally and much data for having flexible movement. To realize such a humanoid robot, distributed control method is preferred to the centralized one since it gives a compactness, modularity and flexibility for the controllers. For organizing distributed control system of a humanoid robot, a control processor on a board is needed to individually control the joint motor and communication technology between the processors is required to transmit its information within control time. The processor is DSP-based processor and includes CAN network on a chip. It shares the computational load such as monitoring the sensor information and controlling the actuator between each of modules. In this paper, the communication architecture is suggested and its message protocol are discussed including message structure, time consumption for transmission, and controller structure at the view of distributed control for a humanoid robot. All of the sequence are simulated with Matlab and then verified with real walking experiment by ISHURO.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.10a
• /
• pp.153-156
• /
• 2009

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability ($0.22^{\circ}/hr$) and scale factor stability, extremely low angle random walk ($0.07^{\circ}/\sqrt{hr}$) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The CIC type of decimation block only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2002.04a
• /
• pp.241-244
• /
• 2002

본 논문은 Post-PC 에 사용되는 DSP 프로세서 기반 디지털 카메라의 효율적이고 소형화된 영상 처리 플랫폼 설계에 대해 설명한다. 제한된 소량의 기억장치를 갖는 내장형 시스템의 제약조건을 만족시키기 위해서 제안된 플랫폼은 블록 처리의 개념을 사용하여 입력 영상을 처리한다. 먼저 입력 영상이 적당한 수의 데이터 블록으로 나누어진다. 그리고 나서 영상 블록들은 일련의 블록 기반 함수들에 의해서 처리된다. 처리된 블록들은 다시 하나의 결과 영상으로 모아진다. 블록 처리는 요구되는 메모리 크기를 줄여줄 뿐만 아니라 multithreading 과 병렬 처리를 통한 더 빠른 수행을 가능하도록 해준다. 플랫폼을 구성하는 대부분의 함수들은 이러한 블록 처리의 장점을 살려서 일련의 영상 블록들을 처리한다. 소개되는 플랫폼은 특화된 하드웨어를 사용하지 않고 사용자의 요구에 맞는 또다른 영상 처리와 압축 기법을 추가하는 것이 가능하게 해준다.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.10 no.2
• /
• pp.162-168
• /
• 2005

In this paper, a digital current mode control is designed for the power converter applications. The designed digital current mode controller is derived analytically from the continuous time small signal model of the power converters. Due to the small signal model based derivations of the control law, the designed control method can be applicable to boost, buck, and buck-boost converters. It is also proven that the controlled power converter employing the designed digital current mode controller is always stable regardless of an operating conditions. In order to show the usefulness of a designed controller, experiments are carried out using a 16bit DSP micro-processor, TMS320LF2406A.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.797-802
• /
• 2020

In this paper, we presents the design and implementation results of the FFT processor, which supports 4096 points of operation with less memory by sharing several memory used in the base-4 systolic array FFT processor into one memory. Sharing memory provides the advantage of reducing the area, and also simplifies the flow of data as I/O of the data progresses in one memory. The presented FFT processor was implemented and verified on the FPGA device. The implementation resulted in 51,855 CLB LUTs, 29,712 CLB registers, 8 block RAM tiles and 450 DSPs, and confirmed that the memory area could be reduced by 65% compared to the existing base-4 systolic array structure.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.116-119
• /
• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• Proceedings of the KIEE Conference
• /
• 2003.07d
• /
• pp.2218-2220
• /
• 2003

현대 산업현장에서 80%이상 사용되는 PID(proportional integral derivative) 제어기는 제어성, 적응성, 제어이득 조정 등의 특정이 있어나 제어 대상에 대한 PID 제어 계수를 경험적 방법인 수동으로 동조해야하는 문제점이 있다. 이를 개선하기 위해 본 논문에서 PID제어기의 최적 자동동조를 위한 릴레이 동조 방법을 제안한다. 기존의 한계감도법과 과도응답 법으로 초기계수를 결정하는 방법보다 유연성과 적용성이 높고, 이를 마이크로프로세서(DSP : TMS-320C32)에 적용하여 소프트웨어적으로 릴레이의 기능이 이루어지도록 설계했다. 이는 Ziegler-Nichols 계수조정법이 갖는 적용대상의 제약성을 극복한 방법이며, 릴레이에 의해 출력을 강제 진동시키고 출력의 진폭과 주기를 이용하여 PID 계수를 조정하고, 또 상대안정성의 척도인 위상여유를 고려하므로 시스템의 상대안정성과 견실성을 향상시킬 수 있음을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.11a
• /
• pp.322-325
• /
• 2011

스테레오 비전 시스템에서 전통적인 매칭 알고리즘으로 SAD(Sum of Absolute Differences), SSD(Sum of Squared Differences), NCC(Normalized Cross Correlation) 등 다양한 알고리즘이 존재한다. 그러나 하드웨어로 실시간 처리를 위한 시스템을 구현하기 위해서는 리소스가 한정 되어있다는 제약 때문에 많은 연구에서 SAD 혹은 RT(Rank Transform), CT(Census Transform)를 많이 사용하게 된다. FPGA 내부에는 BRAM(Block RAM)과 MAC(multiply-accumulator)인 DSP슬라이스가 이미 존재한다. 본 논문에서는 BRAM과 DSP로직을 활용해서 전통적인 매칭 알고리즘 중에서 연산기 사용이 가장 많은 NCC를 FPGA로 실시간 처리 가능한 하드웨어 구조를 제안한다.