• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.57-58
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• 2010

This paper proposes maximum torque control of IPMSM drive using optimal current. This control method is applicable over the entire speed range which considered the limits of the inverter's current and voltage rated value. For each control mode, a condition that determines the optimal d-axis current $i_d$ for maximum torque operation is derived. This paper considers the design and implementation of novel technique of high performance speed control for IPMSM using multi-MFC and ANN controller. Also, this paper proposes maximum control of IPMSM drive using approximation method. This method is decreased the burden of digital signal process(DSP) in calculation of optimal current. This paper proposes the analysis results to verify the effectiveness of the MFC and ANN controller. Also it verifies the validity of maximum torque control of IPMSM drive with optimal current.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1460-1468
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• 2000

The goal of this research is the real-time implementation of MPEG-1 Layer III audio decoder using the fixed-point digital signal processor of TMS320C6201 The main job for this work is twofold: one is to convert floating-point operation in the decoder into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real-time with memory size as small as possible. We, especially, devote much time to the descaling module in the decoder for conversion of floating-point operation into fixed-point operation with high accuracy. The inverse modified cosine transform(IMDCT) and synthesis polyphase filter bank modules are optimized in order to reduce the amount of computation and memory size. After the optimization process, in this paper, the implemented decoder uses about 26% of maximum computation capacity of TMS320C6201. The program memory, data ROM, data RAM used in the decoder are about 6.77kwords, 3.13 kwords and 9.94 kwords, respectively. Comparing the PCM output of fixed-point computation with that of floating-point computation, we achieve the signal-to-noise ratio of more than 60 dB. A real-time operation is demonstrated on the PC using the sound I/O and host communication functions in the EVM board.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.296-306
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• 2003

In this paper, algorithm for non-iterative decoding method is proposed and fractal image decoder based on non-iterative fractal decoding algorithm used general purpose digital signal processors is designed and implemented. The algorithm is showed that the attractor image can be obtained analytically whe n the image is encoded using the fractal algorithm proposed by Monro and Dudbridge, in which the corresponding domain block for a range block is fifed. Using the analytical formulas, we can obtain the attractor image without iteration procedure. And we get general formulas of obtained analytical formulas. Computer simulation results for various test images show that we can increase the image decoding speed by more than five times when we use the analytical formulas compared to the previous iteration methods. The fractal image decoder contains two ADSP2181's and perform image decoding by three stage pipeline structure. The performance tests of the implemented decoder is elapsed 31.2ms/frame decoding speed for QCIF data when all the frames are decoded. The results enable us to process the real-time fractal decoding over 30 frames/sec.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.