• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.45-48
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• 1999

The demands of WLAN(Wireless Local Area Network) systems increase rapidly in whole society and this phenonenon has been expected that WLAN wi11 substitute for wired-LAN. The FHSS(Frequency Hopped Spread Spectrum) method using the WLAN is changed to the performance of Frequency synthesizer. In this paper, we proposed pipeline-accumulator using ring-counter method instead of constant accumulator that has demerits of size and power consumption. Designed DDFS generated operating frequency of 167MHz and maximum output frequency of 83.5MHz.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.267-270
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• 1999

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. In the case that ROM is used for sinusoidal value calculation, reducing the size of ROM is significant. So the power consumption is affected mostly by its bit width. In the proposed method, the ROM bit width is reduced by 1 bit using the phase subtraction and the approximation. The spurious level is better than 80㏈c and the power consumption estimated is 510㎼/MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1349-1359
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• 1998

In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1179-1182
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• 2016

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. This method use the sine-linear phase difference method and differential PCM. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine-linear phase difference is saved by the ROM1 of the $2^N$ sample period. The ROM2 save the difference between the original sine-linear phase difference value and the saved sample value of the ROM1. The ROM compression ratio of 37% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1053-1056
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• 2005

This paper proposes a design technique of DDS (Direct Digital Synthesizer) to reduce the ROM size, and also describes the procedure of the implementation of the technique. Unlike other techniques suggested so far, the proposed technique is able to reduce the ROM size to a great extent with minimal hardware overheads. The frequencies of the signal synthesized by the implemented DDS accurately changed with the applied frequency control words.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.946-949
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• 2003

In this paper, a DDFS(Direct Digital Frequency Synthesis)chip has been designed focusing on the reduction of ROM size and implemented using FPGA. When calculating the sine value for the input phase value, we used the Taylor series expansion approximation method to reduce the number of addresses of ROM. We also used the piecewise straight line approximation method, ie, the stored value int the ROM is the difference of the sine value and the straight line approximation. Using this method, we could reduce four bits for each ROM data.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.35-46
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• 1999

A derotator VLSI which compensates for the frequency and phase errors of a received signal in digital communication systems was developed employing a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. Since a derotator needs only small phase error accumulation, a fast direction sequence generation method which exploits the linearity of the arctangent function in small angles is utilized in order to enhance the operating speed. The chip was designed and implemented using a $0.6\mu\textrm{m}$ triple metal CMOS process by the full custom layout method. The whole chip size is $6.8\textrm{mm}^2$ and the maximum operating frequency is 25 MHz.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.128-133
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• 1998

This paper is study on performance analysis of modulator using direct digital frequency synthesizer of Initial Clock Accumulating Method. It has been generally used for PLL or digital frequency synthesizing method to be synthesizd randomly chosen frequency state. In order to improve disadvantage of two methods, we constructed modulator system using DDFS of Initial Clock Accumulating Method. We also confirmed the coherence frequency hopping state and possibility of phase control. The results obtained from the experiments are as follows; First, the synthesized output frequency is proportional to the sampling frequency, according to index, K. Second, the difference of the gain between the basic frequency and the harmonic frequencies was more than 50 [dB], that is, this means facts that is reduced the harmonic frequency factor. Third, coherence frequency hopping state is confirmed by PN code sequence. Here, we confirmed the proposed method cut switching time, this verify facts that is the best characteristic of the frequency hopping. We also verified the fact that the phase varies as the adder is operated set or reset.

• Smart Structures and Systems
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• v.6 no.7
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• pp.835-849
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• 2010

This study investigated propagation characteristics of piezo-activated guided waves in an aluminium rectangular-section tube for the purpose of damage identification. Changes in propagating velocity and amplitude of the first wave packet in acquired signals were observed in the frequency range from 50 to 250 kHz. The difference in guided wave propagation between rectangular- and circular-section tubes was examined using finite element simulation, demonstrating a great challenge in interpretation of guided wave signals in rectangular-section tubes. An active sensor network, consisting of nine PZT elements bonded on different surfaces of the tube, was configured to collect the wave signals scattered from through-thickness holes of different diameters. It was found that guided waves were capable of propagating across the sharp tube curvatures while retaining sensitivity to damage, even that not located on the surfaces where actuators/sensors were attached. Signal correlation between the intact and damaged structures was evaluated with the assistance of a concept of digital damage fingerprints (DDFs). The probability of the presence of damage on the unfolded tube surface was thus obtained, by which means the position of damage was identified with good accuracy.