• Title/Summary/Keyword: DC Capacitors

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The Characteristics of (Ba,Sr)$TiO_3$ Thin Films Etched With The high Density $BCl_3/Cl_2$/Ar Plasma ($BCl_3/Cl_2$/Ar 고밀도 플라즈마에서 (Ba,Sr)$TiO_3$ 박막의 식각 특성에 관한 연구)

  • Kim, Seung-Bum;Kim, Chang-Il
    • Proceedings of the KIEE Conference
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    • 1999.11d
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    • pp.863-866
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    • 1999
  • (Ba,Sr)$TiO_3$ thin films have attracted groat interest as new dielectric materials of capacitors for ultra-large-scale integrated dynamic random access memories (ULSI-DRAMs) such as 1 Gbit or 4 Gbit. In this study, inductively coupled $BCl_3/Cl_2$/Ar plasmas was used to etch (Ba,Sr)$TiO_3$ thin films. RF power/dc bias voltage = 600 W/-250 V and chamber pressure was 10 mTorr. The $Cl_2/(Cl_2+Ar)$ was fixed at 0.2, the (Ba,Sr)$TiO_3$ thin films were etched adding $BCl_3$. The highest (Ba,Sr)$TiO_3$ etch rate is 480$\AA/min$ at 10 % $BCl_3$ adding to $Cl_2$/Ar. The characteristics of the plasmas were estimated using optical emission spectroscopy (OES). The change of Cl, B radical density measured by OES as a function of $BCl_3$ percentage in $Cl_2$/Ar. The highest Cl radical density was shown at the addition of 10% $BCl_3$ to $Cl_2$/Ar. To study on the surface reaction of (Ba,Sr)$TiO_3$ thin films was investigated by XPS analysis. Ion enhancement etching is necessary to break Ba-O bond and to remove $BaCl_2$. There is a little chemical reaction between Sr and Cl, but Sr is removed by physical sputtering. There is a chemical reaction between Ti and Cl, and Tic14 is removed with ease. The cross-sectional of (Ba,Sr)$TiO_3$ thin film was investigated by scanning electron microscopy (SEM), the etch slope is about $65\;{\sim}\;70$.

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Breakdown Properties in Physiological Saline by High Voltage Pulse Generator

  • Byeon, Yong-Seong;Song, Ki-Baek;Uhm, Han-Sup;Shin, Hee-M.;Choi, Eun-Ha
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.08a
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    • pp.333-333
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    • 2011
  • We have investigated the breakdown properties in liquids by high voltage pulse system. High voltage pulse power system is consisted of the Marx-generator with two capacitors (0.5 ${\mu}F$, withstanding voltage is 40 kV), to which the charging voltage can be applied to maximum 30 kV DC, spark gap switch and charging resistor of 20 $M{\Omega}$. We have made use of tungsten pin electrodes of anode-cathode (A-K), which are immersed into the liquids. The breakdown voltage and current signals are measured by high voltage probe (Tektronix P6015A) and current monitor (IPC CM-1.S). Especially the high speed breakdown or plasma propagation characteristics in the pulsed A-K gap have been investigated by using the high speed ICCD camera. We have measured the electron temperature through the Boltzmann plot method from the breakdown spectrums. Here the A-K gap has been changed by 1 mm, 2 mm, and 3 mm. The used liquids are distilled water and solution of salt (0.9 %). The output voltage and current signals at breakdown in distilled water are shown to be bigger than those in saline solution. The breakdown voltage and current characteristics in liquids will be discussed in accordance with A-K gap distances. It is also found that the electron temperatures and plasma densities in liquids are decreased in conformity with A-K gap.

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A Study on Improving Power Quality by Real-time Reactive Power/Power Factor Compensating Equipment at Substation in Marshalling Yard (전기철도 차량기지 변전소의 실시간 무효전력/역률 보상설비 적용에 따른 전력품질 개선에 관한 연구)

  • Park, Soo-Cheol;Song, Joong-Ho
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.20 no.10
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    • pp.58-67
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    • 2006
  • In this paper, real-time reactive power/power factor compensating equipment is suggested for improving power quality at electrical railway's substation in marshalling yard and designing optimal capacity of compensating equipment for actual apply at current marshalling yard. For this purpose, several kind of real-time reactive power/power factor compensating equipments are introduced and SVG(Static Var Generator) as optimal compensating equipment that is suitable for load characteristics of substation in marshalling yard is suggested. This paper shows proper simulations by suggested equipment using PSIM software and describe basic compensating principle and simulation results. Optimal capacity design for applying current marshalling yard is based on real measured power quality data. Power quality improvement that is performed by SVG as real-time reactive power/power factor compensating equipment is estimated at electrical railway's substation in marshalling yard. As reference, real-time reactive power/power factor compensating equipment is composed by voltage source inverter and DC capacitors.

Minimization of a CW CO2 Laser Output Ripple by using High Frequency Resonance Phenomena (고주파 공진현상을 이용한 CW CO2 레이저의 출력리플 최소화)

  • Sikander, Sakura;Kwon, Min-Jae;Kim, Hee-Je;Lee, Dong-Gil;Xu, Guo-Cheng
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.62 no.6
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    • pp.798-802
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    • 2013
  • In a conventional DC power supply used for CO2 laser, the circuit elements such as a rectifier bridge, a current-limiting resistor, a high voltage switch, energy storage capacitors ans a high-voltage isolation transformer using high turn ratio are necessary. Consequently, those supplies are expensive and require a large space. Thus, laser resonator and power supply should be optimally designed. In this paper, we propose a new power supply using high frequency resonance phenomena for CW(Continuous wave) CO2 laser (maximum output of 23W with discharge length of 450mm). It consists of a transformer including leakage inductance, magnetizing inductance and half-bridge converter, a three-stage Cockcroft-Walton and PFC(Power factor correction) circuit. The output ripple voltage can be controlled the minimum of 0.24% under the high frequency switching of 231kHz. Furthermore, the output efficiency was improved to 16.4% and the laser output stability of about 5.6% was obtained in this laser system.

The Study of Method about the Multi-channel Simultaneous Measurement for Measuring the I-V Curve of Photovoltaic Array (태양광 어레이 I-V 곡선 측정을 위한 다채널 동시 측정방법에 관한 연구)

  • Park, Yu-Na;Jang, Gil-Soo;Ko, Suk-Whan;Kang, Gi-Hwan;So, Jung-hun;Jung, Young-Seok;Ju, Young-Chul;Hwang, Hye-Mi;Song, Hyung-Jun
    • Journal of the Korean Solar Energy Society
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    • v.37 no.4
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    • pp.23-33
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    • 2017
  • A great deal of study for loss reduction of photovoltaic system is conducted currently. It is hard to distinct the fault of photovoltaic system with the naked eye. For that reason, it is essential to repair and maintain the PV system by monitoring the system. The fault of individual modules can cause the huge loss of the entire system because of the mismatch. Therefore, the method of diagnosing the PV array is necessary by measuring the multi-channel arrays simultaneously. In this paper, it is presented the method of measuring I-V curve of multi-channel arrays simultaneously by using the charge and discharge characteristics of capacitor. Generated DC power at PV arrays is charged and discharged at the capacitors in a moment. By measuring the charged voltage and current, it is possible to diagnose of performance of PV arrays.

Impedance Spectroscopy Models for X5R Multilayer Ceramic Capacitors

  • Lee, Jong-Sook;Shin, Eui-Chol;Shin, Dong-Kyu;Kim, Yong;Ahn, Pyung-An;Seo, Hyun-Ho;Jo, Jung-Mo;Kim, Jee-Hoon;Kim, Gye-Rok;Kim, Young-Hun;Park, Ji-Young;Kim, Chang-Hoon;Hong, Jeong-Oh;Hur, Kang-Heon
    • Journal of the Korean Ceramic Society
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    • v.49 no.5
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    • pp.475-483
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    • 2012
  • High capacitance X5R MLCCs based on $BaTiO_3$ ceramic dielectric layers exhibit a single broad, asymmetric arc shape impedance and modulus response over the wide frequency range between 1 MHz to 0.01 Hz. Analysis according to the conventional brick-layer model for polycrystalline conductors employing a series connection of multiple RC parallel circuits leads to parameters associated with large errors and of little physical significance. A new parametric impedance model is shown to satisfactorily describe the experimental spectra, which is a parallel network of one resistor R representing the DC conductivity thermally activated by 1.32 eV, one ideal capacitor C exactly representing bulk capacitance, and a constant phase element (CPE) Q with complex capacitance $A(i{\omega})^{{\alpha}-1}$ with ${\alpha}$ close to 2/3 and A thermally activated by 0.45 eV or ca. 1/3 of activation energy of DC conductivity. The feature strongly indicate the CK1 model by J. R. Macdonald, where the CPE with 2/3 power-law exponent represents the polarization effects originating from mobile charge carriers. The CPE term is suggested to be directly related to the trapping of the electronic charge carriers and indirectly related to the ionic defects responsible for the insulation resistance degradation.

Prediction of Impedance Characteristics of Multi-Layer Ceramic Capacitor Based on Coupled Transmission Line Theory (결합 전송선로 이론을 이용한 적층 세라믹 커패시터의 임피던스 특성 예측)

  • Jeon, Jiwoon;Kim, Jonghyeon;Pu, Bo;Zhang, Nan;Song, Seungjae;Nah, Wansoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.2
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    • pp.135-147
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    • 2015
  • With the miniaturization and digitalization of electronics industry, demand for Multi-Layer Ceramic Capacitor(MLCC) has increased steadily because of its various applications such as DC Blocking, Decoupling and Filtering etc. The modeling techniques of MLCC has been studied for a long time but most of these modeling method can only be applied after measurement and this has some losses of material, time in both production stage and measurement stage. This paper proposes the modeling method which can predict the frequency characteristics of MLCC from structure data and material data in design stage. The impedance of N-Layer Capacitor can be expressed in differential mathematical form based on coupled transmission line equations. By using this formula, we can predict the impedance of MLCC. As a result, proposed modeling is correspond with simulation, and it takes much less time to obtain the result than the simulation.

Integrated Circuit of a Peak Detector for Flyback Converter using a 0.35 um CMOS Process (0.35 um CMOS 공정을 이용한 플라이백 컨버터용 피크검출기의 집적회로 설계)

  • Han, Ye-Ji;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.7
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    • pp.42-48
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    • 2016
  • In this paper, a high-precision peak detector circuit that detects the output voltage information of a fly-back converter is proposed. The proposed design consists of basic analog elements with only one operational amplifier and three transistors. Because of its simple structure, the proposed circuit can minimize the delay time of the detection process, which has a strong impact on the precision of the regulation aspect of the fly-back converter. Furthermore, by using an amplifier and several transistors, the proposed detector can be fully integrated on-chip, instead of using discrete circuit elements, such as capacitors and diodes, as in conventional designs, which reduces the production cost of the fly-back converter module. In order to verify the performance of the proposed scheme, the peak detector was simulated and implemented by using a 0.35 m MagnaChip process. The gained results from the simulation with a sinusoidal stimulus signal show a very small detection error in the range of 0.3~3.1%, which is much lower than other reported detecting circuits. The measured results from the fabricated chip confirm the simulation results. As a result, the proposed peak detector is recommended for designs of high-performance fly-back converters in order to improve the poor regulation aspect seen in conventional designs.

A Study on the Etching Mechanism of $(Ba, Sr)TiO_3$ thin Film by High Density $BCl_3/Cl_2/Ar$ Plasma ($BCl_3/Cl_2/Ar$ 고밀도 플라즈마에 의한 $(Ba, Sr)TiO_3$ 박막의 식각 메커니즘 연구)

  • Kim, Seung-Bum;Kim, Chang-Il
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.11
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    • pp.18-24
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    • 2000
  • (Ba,Sr)$TiO_3$ thin films have attracted great interest as new dielectric materials of capacitors for ultra-large-scale integrated dynamic random access memories (ULSI-DRAMs) such as 1 Gbit or 4 Gbit. In this study, inductively coupled $BCl_3/Cl_2/Ar$ plasmas was used to etch (Ba,Sr)$TiO_3$ thin films. RF power/dc bias voltage=600 W/-250 V and chamber pressure was 10 mTorr. The $Cl_2/(Cl_2+Ar)$ was fixed at 0.2 the (Ba,Sr)$TiO_3$ thin films were etched adding $BCl_3$. The highest (Ba,Sr)$TiO_3$ etch rate is $480{\AA}/min$ at 10 % $BCl_3$ to $Cl_2/Ar$. The change of Cl, B radical density measured by optical emission spectroscopy(OES) as a function of $BCl_3$ percentage in $Cl_2/Ar$. The highest Cl radical density was shown at the addition of 10% $BCl_3$ to $Cl_2/Ar$. To study on the surface reaction of (Ba, Sr)$TiO_3$ thin films was investigated by XPS analysis. Ion bombardment etching is necessary to break Ba-O bond and to remove $BaCl_2$. There is a little chemical reaction between Sr and Cl, but Sr is removed by physical sputtering. There is a chemical reaction between Ti and Cl, and $TiCl_4$ is removed with ease. The cross-sectional of (Ba,Sr)$TiO_3$ thin film was investigated by scanning electron microscopy (SEM), the etch slope is about 65~70$^{\circ}$.

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Design of a Fourth-Order Sigma-Delta Modulator Using Direct Feedback Method (직접 궤환 방식의 모델링을 이용한 4차 시그마-델타 변환기의 설계)

  • Lee, Bum-Ha;Choi, Pyung;Choi, Jun-Rim
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.6
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    • pp.39-47
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    • 1998
  • A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

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