• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.39-47
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• 2023

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.570-575
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• 2012

In a wireless communication RF transmitter, the output of a quadrature modulator (QM) is distorted by not only the linear imperfection features such as in/quadrature-phase (I/Q) input gain imbalance, local phase imbalance, and local gain imbalance but also the nonlinear imperfection features such as direct current (DC) offset and mixer nonlinearity related to in-band spurious signal. In this paper, we propose the unified QM model to analyze the combined effects of the linear and nonlinear imperfection features on the performance of the QM. The unified QM model consists of two identical nonlinear systems and modified I/Q inputs based on the two-port nonlinear mixer model. The unified QM model shows that the output signals can be expressed by mixer circuit parameters such as intercept point and gain as well as the imperfection features. The proposed approach is validated by not only simulation but also measurement.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2000.02a
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• pp.91-94
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• 2000

We fabricated resistive super- conducting fault current limiters (SFCL) based on YBCO thin films grown on 2" diameter $Al_{2}O_{3}$ substrates. Two SFCLs with nearly identical properties. two SFCLs with nearly identical properties were connected in series to investigate simultaneous quenching. There was a difference of several half cycles in their quench starting time, although the difference was not more than 0.1 msec when they were operated separately. This imbalance was removed by connecting a shunt resistor to an SFCL in parallel. Increased power input at high voltages also reduced the initial imbalance in power dissipation. Further efforts on the simultaneous quench in SFCLs connected in series are on the way through methods such as the artificial control of quench speed.peed.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.239-241
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• 2003

When superconductors are combined with normal conductor as a parallel electric circuit, imbalance of the applied current is happened. For the accurate parameters of the circuit, it is needed to measure the current of the circuit under LN2 condition. In this case, the measurement using Rogowski coil, which is not that affected by changing temperature, can be a method. In this study, using 2 Rogowski coil, the measurement of current was conducted under the condition that is room and LN2 temperature respectively.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1551-1564
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• 2016

The high penetration level of inverter-based distributed generation (DG) power plants is challenging the low-voltage ride-through requirements, especially under unbalanced voltage sags. Recently, a flexible injection of both positive- (PS) and negative-sequence (NS) reactive currents has been suggested for the next generation of grid codes. This can enhance the ancillary services for voltage support at the point of common coupling (PCC). In light of this, considering distant grid faults that occur in a mainly inductive grid, this paper proposes a complete voltage support control scheme for the interface inverters of medium or high-rated DG power plants. The first contribution is the development of a reactive current reference generator combining PS and NS, with a feature to increase the PS voltage and simultaneously decrease the NS voltage, to mitigate voltage imbalance. The second contribution is the design of a voltage support control loop with two flexible PCC voltage set points, which can ensure continuous operation within the limits required in grid codes. In addition, a current saturation strategy is also considered for deep voltage sags to avoid overcurrent protection. Finally, simulation and experimental results are presented to validate the effectiveness of the proposed control scheme.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.11
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• pp.737-741
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• 2000

We fabricated resistive superconducting fault current limiters (SFCL) based on YBCO thin films grown on 2-inch diameter $Al_2O_3$ substrates. Two SFCLs with nearly identical properties were connected in series to investigate simultaneous quench. There was a slight difference in the rate of voltage increase between two SFCL units when they were operated independently. This difference resulted in significantly imbalanced power dissipation between the units. This imbalance was removed by connecting a shunt resister to an SFCL in parallel. The appropriate values of shunt resistance were 80 ${\Omega}$ at 75 $V_rms$ and 110 ${\Omega}$ at 120 $V_rms$, respectively. Increased power input at high voltages also reduced the initial imbalance in power dissipation, but with increase in film temperature to higher than 200 K.

• Journal of Power Electronics
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• v.19 no.1
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• pp.89-98
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• 2019

This paper analyzes the input side performance of a conventional three-phase to single-phase matrix converter (3-1MC). It also presents the input-side waveform quality under this topology. The suppression of low-frequency input current harmonics is studied using the 3-1MC plus capacitance compensation unit. The constraint between the modulation function of the output and compensation sides is analyzed, and the relations among the voltage utilization ratio and the output compensation capacitance, filter capacitors and other system parameters are deduced. For a 3-1MC without large-capacity energy storage, the system performance is susceptible to input voltage imbalance. This paper decouples the inner current of the 3-1MC using a Lyapunov function in the input positive and negative sequence bi-coordinate axes. Meanwhile, the outer loop adopts a voltage-weighted synthesis of the output and compensation sides as a cascade of control objects. Experiments show that this strategy suppresses the low-frequency input current harmonics caused by input voltage imbalance, and ensures that the system maintains good static and dynamic performances under input-unbalanced conditions. At the same time, the parameter selection and debugging methods are simple.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2001.02a
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• pp.176-177
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• 2001

Three nearly identical superconducting fault current limiters (SFCLs) were connected in series to increase the voltage ratings. A slight difference in the quench starting point of individual SFCL units produced significantly imbalanced power distribution when connected in series. The imbalance was successfully removed by connecting a shunt resistor to one SFCL in parallel. 1.2 kV SFCL was designed with five current limiting elements and two or three shunt resistors.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.2
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• pp.301-307
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• 2009

In the paralleled converter module with peak current mode control, current imbalance appears when the voltage controllers with integral control of converter module are not exactly identical. In this paper, the voltage controller is designed to equal the current command of each converter module using the current command bus. The current balance controller is also proposed to balance the average currents of converter modules with imbalaced inductance. It is designed to have good transient response. Proposed method is implemented with the paralleled 2-module and 4-module boost converters with imbalanced inductance. Experimental results verify the performance of current share during both steady and transient states of converter.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.6
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• pp.31-38
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• 2003

Among mitigation techniques for electric and magnetic field (EMF) from an overhead transmission line a passive loop is a way that can be cheap and easily installed on the existing towers and have a satisfactory effect as well. However current induced in the passive loop causes transmission power loss and the phase imbalance increases since geometrical asymmetry of the transmission lines becomes larger. So in order to evaluate the power loss and the phase imbalance due to a passive loop, this paper represent a 345[kV] 1-circuit flat type transmission line as asymmetrical 3-phase distributed parameter line model where the effect of a passive loop is embedded in the line parameters, and then formulates differential equations. By solving these equations voltages and currents of each phase at receiving end become known. We find out that power losses occur differently at each phase and positive sequence component decreases at receiving end while negative sequence component increase. In general phase imbalance due to a passive loop is slight, but it increases in proportional to the induced current and length of section where the passive loop is installed. Thus the phase imbalance should be included in terms of cost for introducing a passive loop.