• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.30 no.6
• /
• pp.467-478
• /
• 2019

This paper describes the development and measurement results of a wide-band planar active phase array antenna system for an electronic warfare jamming transmitter. The system is designed as an $8{\times}8$ triangular lattice array using a $45^{\circ}$ slant wide-band antenna. The 64-element transmission channel is composed of a wide-band gallium nitride(GaN) solid state power amplifier and a gallium arsenide(GaAs) multi-function core chip(MFC). Each GaAs MFC includes a true-time delay circuit to avoid a wide-band beam squint, a digital attenuator, and a GaAs drive amplifier to electronically steer the transmitted beam over a ${\pm}45^{\circ}$ azimuth angle and ${\pm}25^{\circ}$ elevation angle scan. Measurement of the transmitted beam pattern is conducted using a near-field measurement facility. The EIRP of the designed system, which is 9.8 dB more than the target EIRP performance(P), and the ${\pm}45^{\circ}$ azimuth and ${\pm}25^{\circ}$ elevation beam steering fulfill the desired specifications.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.7
• /
• pp.1071-1077
• /
• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.