• 대한전자공학회논문지SD
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• 제37권3호
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• pp.27-33
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• 2000

선택성을 향상시키기 위해서 BPSG(Borophosphosilicate glass) 위에 형성한 TiN 패턴을 로(furnace) 열처리와 질소 플라즈마 처리를 한 후 유기 화학 기상 증착법(MOCVD； Metal Organic Chemical Vapor Deposition)으로 구리 박막을 증착하였다. 먼저 650℃∼750℃에서 열처리한 후 150℃에서 구리 박막을 증착시켰을 때 750℃에서 열처리한 경우 TiN 표면 위에만 선택적으로 구리 증착이 일어났다. 질소 플라즈마 처리를 한 경우도 마찬가지로 BPSG 위에 구리 핵 형성이 억제됨을 알 수 있었다. 플라즈마 처리 온도를 증가시킬수록 BPSG 위의 구리 핵 형성이 더 효과적으로 억제되었다. 열처리와 플라즈마 처리 후 증착된 기판 표면을 TOF-SIMS(Time-of-Flight Secondary Ion Mass Spectrometry)로 분석하였을 때 플라즈마 처리가 BPSG 표면의 구리 증착 작용기인 0-H(hydroxyl)기를 제거하여 구리의 선택성이 향상되었다고 해석하였다.

• The Korean Journal of Ceramics
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• 제4권3호
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• pp.222-226
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• 1998

$Cu_3N$ film deposited on silicon oxide substrate by r.f. reactive sputtering technique. Synthesis and properties of copper nitride film were investigated for its possible application to Cu metallization as adhesive interlayer between copper and $SiO_2. Cu_3N$ film was synthesized at the substrate temperature ranging from $100^{\circ}C$ to $200^{\circ}C$ and at nitrogen gas ratio above $X_{N2}=0.4. Cu_3N, CuN_x$, and FGM-structured $Cu/CuN_x$ films prepared in this work passed Scotch-tape test and showed improved adhesion property to silicon oxide substrate compared with Cu film. Electrical resistivity of copper nitride film had a dependency on its lattice constant and was ranged from 10-7 to 10-1 $\Omega$cm. Copper nitride film was, however, unstable when it was annealed at the temperature above $400^{\circ}C$.

• 한국섬유공학회:학술대회논문집
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• 한국섬유공학회 2007년도 학술발표회 논문집
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• pp.255-256
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• 2007

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• Transactions on Electrical and Electronic Materials
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• 제10권3호
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• pp.71-74
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• 2009

Electroplated Cu is a cost efficient metallization method in microelectronic packaging applications. Typically in 3-D chip staking technology, utilizing through silicon via (TSV), electroplated Cu metallization is inevitable for the throughput as well as reducing the cost of ownership (COO).To achieve a comparable film quality to sputtering or CVD, a pre-cleaning process as well as plating process is crucial. In this research, atmospheric plasma is employed to reduce the usage of chemicals, such as trichloroethylene (TCE) and sodium hydroxide (NaHO), by substituting the chemical assisted organic cleaning process with plasma surface treatment for Cu electroplating. By employing atmospheric plasma treatment, marginally acceptable electroplating and cleaning results are achieved without the use of hazardous chemicals. The experimental results show that the substitution of the chemical process with plasma treatment is plausible from an environmentally friendly aspect. In addition, plasma treatment on immersion Sn/Cu was also performed to find out the solderability of plasma treated Sn/Cu for practical industrial applications.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.91.2-91.2
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• 2010

The use of plated front contact for metallization of silicon solar cell may alternative technologies as a screen printed and silver paste contact. This technologies should allow the formation of contact with low contact resistivity a high line conductivity and also reduction of shading losses. The better performance of Ni/Cu contacts is attributed to the reduced series resistance due to better contact conductivity of Ni with Si and subsequent electroplating of Cu on Ni. The ability to pattern narrower grid lines for reduced light shading combined with the lower resistance of a metal silicide contact and improved conductivity of plated deposit. This improves the FF as the series resistance is deduced. This is very much required in the case of low concentrator solar cells in which the series resistance is one of the important and dominant parameter that affect the cell performance. A selective emitter structure with highly dopes regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing. This paper using selective emitter structure technique, fabricated Ni/Cu plating metallization cell with a cell efficiency of 17.19%.

• 한국전기전자재료학회논문지
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• 제24권12호
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• pp.1010-1017
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• 2011

The use of plated front contact for metallization of silicon solar cell may alternative technologies as a screen printed and silver paste contact. This technologies should allow the formation of contact with low contact resistivity a high line conductivity and also reduction of shading losses. A selective emitter structure with highly dopes regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing. When fabricated Ni/Cu plating metallization cell with a selective emitter structure, it has been shown that efficiencies of up to 18% have been achieved using this technology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1262_1263
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• 2009

Programmable Metallization Cell (PMC) is a memory device based on the electrolytical characteristic of chalcogenide materials. In this study, we investigate the nature of thin films formed by photo doping of Ag ions into chalcogenide materials for use in solid electrolyte of programmable metallization cell devices. We were able to do more economical approach by using copper which play an electrolyte ions role. The results imply that a Ag-rich phase separates owing to the reaction of Ag with free atoms from chalcogenide materials.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1352-1355
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• 2004

We have applied front contact metallization of plated nickel and copper for high efficiency passivated emitter rear contact(PERC) solar cell. Ni is shown to be a suitable barrier to Cu diffusion as well as desirable contact metal to silicon. The plating technique is a preferred method for commercial solar cell fabrication because it is a room temperature process with high growth rates and good morphology. In this system, the electroless plated Ni is utilized as the contact to silicon and the plated Cu serves as the primary conductor layer instead of traditional solution that are based on Ti/Pd/Ag contact system. Experimental results are shown for over 20 % PERC cells with the Plated Ni/Cu contact system for good performance at low cost.