• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.1110-1115
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• 1991

Tne mathematical modeling and analysis results of a dataflow logic solving processor(DFLSP) for programmable logic controller(PLC) are proposed in this paper. The logic program language is formalized using a dataflow graph model. From this dataflow graph, the instruction precedence relationship, and deadlock problems, which are major properties of a logic program, are described.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 D
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• pp.948-950
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• 1997

This paper presents a basic interposing logic program to control nuclear power plant. In this paper we select a target control loop among the whole interposing modules, develop logic algorithm and functional software to compose target control loop. After that we carry out V&V(Verification and Validation) into the developed logic program to improve quality and reliability.

• 조명전기설비학회논문지
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• 제28권2호
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• pp.92-99
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• 2014

The paper is related to smart maximum power system based on program logic. Especially, this system compares the total demand power with the target power by using the signal from the digital kilo watt meter. Based on the power information by the maximum power control equipment the consumed future power is anticipated. In addition, through consumed future power the controllable target power is set, and it applies on the maximum power control equipment. User or manager would control the load efficiently through the simple programming which could control load based on the control sequence and relay. To begin with the conventional maximum power control algorithm is surveyed, and the smart maximum power control system based on program logic is used, and the new algorithm from full load to proportion shut down is proposed by using PLC program. the validity of the proposed control scheme is investigated by both simulation results.

• 한국시뮬레이션학회논문지
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• 제15권1호
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• pp.11-17
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• 2006

본 논문에서는 원전 계측제어시스템 구축을 위해 개발된 원전용 PLC 시뮬레이터의 설계 사항에 관해 소개한다. 원전용 계측제어시스템은 원전이라는 특수한 환경과 제약으로 말미암아, 일반적인 시뮬레이터 개발보다 엄격한 요건을 만족해야 한다. 이러한 요건으로는 다양한 테스팅을 통하여 제어 프로그램의 안정성을 보장할 수 있어야 하며, 다수의 계측제어 프로그램들을 고속으로 동시에 실행할 수 있어야 한다. 본 논문에서는 이러한 문제점들을 극복하고자 PLC 제어 프로그램의 컴파일러를 제작하여 C 코드 변환을 하게 된다. 제안한 방법에서는 검증용 상용 도구를 변환된 코드에 적용해 제어 프로그램의 안정성 평가를 할 수 있으며, Compiled-Code 시뮬레이션 기법을 이용하여 고속으로 실행 가능한 시뮬레이터를 자동으로 생성할 수 있다는 장점이 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• 한국산학기술학회논문지
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• 제14권10호
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• pp.5134-5139
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• 2013

복잡한 현대의 제어시스템 설계에 PLC를 사용하면 프로그램은 LD언어나 SFC언어를 사용한다. 대부분은 LD 언어를 사용하지만 최근에는 SFC 언어의 사용빈도수가 높아졌다. SFC 언어는 제어의 흐름을 이해하기가 쉽지만, 조합논리를 표현하는데는 단점을 가지고 있다. SFC언어에서 인터럽트를 처리할 때 인터럽트 요인이 발생하게 되면 메인프로그램을 중지하고 인터럽트 프로그램을 실행하여 프로그램이 종료된 후 메인프로그램으로 복귀하게 된다. 그러면 인터럽트 프로그램이 복잡할수록 메인프로그램 정지시간은 그만큼 길어지게 된다. 본 논문에서는 SFC언어에서 메인프로그램의 휴지시간이 없는 인터럽트 처리방법을 제안하고, 시뮬레이션을 통해 그의 타당성을 확인하였다.

• 제어로봇시스템학회논문지
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• 제12권8호
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• pp.834-841
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• 2006

Recently, many enterprises are installing AMSs(Automated Manufacturing Systems) for their competitive advantages. As the level of automation increases, proper design and validation of control logic is a imperative task for the successful operation of AMSs. However, current discrete event simulation methods mainly focus on the performance evaluation. As a result, they lack the modeling capabilities for the detail logic of automated manufacturing system controller. Proposed in this paper is a method of validation of the controller logic for automated material handling system using an object-oriented design and simulation. Using this method, FA engineers can validate the controller logic easily in earlier stage of system design, so they can reduce the time for correcting the logic errors and enhance the productivity of control program development Generated simulation model can also be used as a communication tool among FA engineers who have different experiences and disciplines.

• 대한전기학회논문지
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• 제40권8호
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.634-638
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• 1990

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP (dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. The proposed DFLSP is adequate for high speed programmable logic controllers and gets rid of data synchronization problem in hardware level. The performance of the proposed DFLSP is analyzed using computer simulations and prototype hardware. With single processing element, the logic solving time is 144 usec per 1K steps of logic program and with eight processing elements, the logic solving time is 23 usec per 1K steps of logic program with reasonable assumptions.