• 대한전자공학회논문지SP
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• 제42권2호
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• pp.143-150
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• 2005

본 논문에서는 OFDM 시스템에 적용하기 위한 새로운 Radix-24 FFT 알고리즘을 제안하고 이 알고리즘을 기반으로 하는 효율적인 파이프라인 FFT 프로세서 구조를 제안한다. Radix-24 알고리즘 기반의 파이프라인 FFT 구조는 Radix-긴 알고리즘 구조와 같은 개수의 곱셈기를 가지고 있으나, 전체 프로그래머블 복소 곱셈기의 절반에 해당하는 곱셈기를 본 논문에서 제안한 CSD(Canonic Signed Digit) 상수 복소 곱셈기로 대체하여 곱셈기의 복잡도를 $30\%$이상 줄이는 효과가 있다. 0.35um CMOS 삼성공정의 합성 시뮬레이션을 통해 제안한 CSD 상수 복소 곱셈기는 기존의 프로그래머블 복소 곱셈기에 비교하여 $60\%$이상 면적효율을 갖는 것으로 분석되었다. 이러한 FFT 구조는 면적과 전력 면에서 높은 효율을 필요로 하는 무선 OFDM 응용분야에 핵심 블록인 큰 포인트 크기를 갖는 FFT 프로세서 설계에 효과적으로 적용될 것이다.

• Journal of Biosystems Engineering
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• 제2권1호
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• pp.49-54
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• 1977

In order to obtain the field efficiency of the power tiller plowing on the various size of and its length-width field tests were performed with 8ps.10ps. power tiller popularly used in the korean rural area, and Satoh 5ps. made in Japan, Land Master 5ps. made in England were tested to compare with the field efficiency of the above power tillers. The results obtained in this tests were as follows ; 1. In considering of the resting time and the refueling time and others, the field efficiency of Satoh was the highest among the power tillers as to be 80%, at the 8ps. power tiller 76.5%, at the 10ps. power tiller 79.3% and the lowest field efficiency was obtained at the Land Master as 75.7%. 2. The field efficiency of the each power tiller increased as the ratio of the length to width of the field was increased. 3. The increasing rate of field efficiency was much bigger in the below the ratio of 5 : 1 but at the upper ratio increased above, the ratio was nearly constant. 4. The field efficiency of the power tiller was higher at the smaller power tiller than the larger, except the Land Master , because of easily operating and turning of the power tiller by virtue of its lighter weight.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.45-48
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• 1999

The demands of WLAN(Wireless Local Area Network) systems increase rapidly in whole society and this phenonenon has been expected that WLAN wi11 substitute for wired-LAN. The FHSS(Frequency Hopped Spread Spectrum) method using the WLAN is changed to the performance of Frequency synthesizer. In this paper, we proposed pipeline-accumulator using ring-counter method instead of constant accumulator that has demerits of size and power consumption. Designed DDFS generated operating frequency of 167MHz and maximum output frequency of 83.5MHz.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2001년도 학술대회논문집
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• pp.65-72
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• 2001

Power system stabilizer act efficiently to damp the electromechanical oscillations in interconnected power systems. This paper presents an algorithm for the optimal parameter selection of a power system stabilizer in two-area power systems with a series HVDC link. This method is one of the classical techniques by allocating properly pole-zero positions to fit as closely as desired the ideal phase lead between the voltage reference and the generator electrical power and by changing the gain to produce a necessary damping torque over the matched frequency range. Control of HVDC converter and inverter are used a constant current loop. Proper parameters of PI controllers are obtain based on the Root-locus technique in other to have sufficient speed and stability margin to cope with charging reference values and disturbance. The small signal stability arid transient stability studies using the PSS parameters obtained from this method show that a natural oscillation frequency of the studycase system is adequately damped. Also the simulation results using the HVDC converter and inverter parameters obtained from this proposed method show proper current control characteristics. The simulation used in the paper was performed by the Power System Toolbox software program based on MATLAB.

• KIEE International Transactions on Power Engineering
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• 제2A권4호
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• pp.131-135
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• 2002

This paper describes a new ultra-fast contingency screening algorithm for on-line TSA without time simulation. All machines are represented in a classical model and the stability index is defined as the ratio between acceleration power during a fault and deceleration power after clearing the fault. Critical clustering of machines is done based on the stability index, and the power-angle curve of the critical machines is drawn assuming that the angles of the critical machines increase uniformly, while those of the non-critical ones remain constant. Finally, the critical clearing time (CCT) is computed using the power-angle curve. The proposed algorithm is tested on the KEPCO system comprised of 900-bus and 230-machines. The CCT values computed with the screening algorithm are in good agreement with those computed using the detailed model and the SIME method. The computation time for screening about 270 contingencies is 17 seconds with 1.2 GHz PC.

• 전자공학회논문지A
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• 제33A권6호
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• pp.164-171
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• 1996

We report the experimental resutls on AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with carbon-doped base structure. To characterize the output power, load-pull mehtod was employed. By characterizing the devices with HP8510C, we extracted the small-signal equivalent circuit. The HBTs were fabricated employing wet mesa etching and lift-off process of ohmic metals. the implementation of polyimide into the fabriction process was accomplished to obtain the lower dielectric constant resultig in significant reduction of interconnect routing capacitance. The fabricated HBTs with an emitter area of 6${\times}14{\mu}m^{2}$ exhibited current gain of 45, BV$_{CEO}$ of 10V, cut-off frequency of 30GHz and power gain of 1 3dBm. To extract the small signal equivalent circuit, the de-embedded method was applied for parasitic parameters and the calculation of circuit equations for intrinsic parameters.

• 전기학회논문지
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• 제65권3호
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• pp.382-387
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• 2016

This paper deals with the assessment of voltage sags regarding the variation of system operating conditions. In general, voltage sag assessment is performed by assuming the constant operating condition throughout the year. However, the assumption can lead to assessment errors in case of considerable changes of system operation condition. This paper presents a method to estimate ESF(expected sag frequency) considering the operating conditions according to the changes of power demand throughout the year.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 A
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• pp.60-63
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• 2004

AGC is widely used to regulate the frequency of power systems. It is also used to control the frequency of Korean Power System. Control strategies depends on systems to which it is applied. Korean Power System consists of one control area and it has no tie-line. In this research, we have developed a simulation tool to confirm AGC dynamics. The developed tool has been verified by two-machine three-bus system. Moreover an AGC control strategy has been suggested to avoid contradiction with governor dynamics. Low pass filter with relatively long time constant showed good regulation performance. This simple strategy is expected to be applied to New EMS in KPX to get reasonable AGC regulation performance.

• 전자공학회논문지
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• 제50권12호
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• pp.3-13
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• 2013

이 논문에서는 OFDM 시스템의 시간 영역 동기를 위한 2가지 방법을 제안한다. 이것은 심벌타이밍 판정의 모호함의 원인이되는 플레토와 사이드로브를 제거하기 위하여 부 심벌간에 1심벌 옵셋을 두고 타이밍 메트릭을 구하는 방법과 플레토 현상을 경감시킬 수 있는 전력감소지수(Reduction Factor, ${\rho}$), 제동상수(Break Constant, ${\beta}_k$) 그리고 심벌이식깊이(Implant Depth, ${\delta}_I$)등의 파라메터를 사용하여 CP(Cyclic Prefix) 구간의 전력을 수정하는 방법이다. 제안된 2가지 방법은 기존에 제안된 심벌타이밍 동기화기법들과 컴퓨터모의시험을 통해서 성능평가가 이루어졌으며, 제안된 방법들은 다중경로의 레일레이 페이딩채널에서 기존의 시스템에 비해서 더 우수한 통계적 특성을 나타내었다.