• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.79-85
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• 2010

In video standards such as H.264/AVC, motion estimation (ME) / compensation (MC) is regarded as a vital component in a video coder as it consumes a large amount of computation resources. The full search technique, which is used in general video codecs, gives the highest visual quality but also has the problem of significant computational load. To solve this problem, many fast algorithm has benn proposed. Among them, NPDS show that can maintain its video quality very close to the full search technique while achieving computation reduction by using a halfway-stop technique in the calculation of block distortion measure. In this paper, we proposed algorithm by determining minimum distortion measure with predictive motion vector and using the new search order. As the result, we can check that the proposed algorithm reduces the computational load 95% in average compared to the full search, respectively with the PSNR lost about 0.04dB.

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1042-1050
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• 2005

This paper proposed a novel low-power video decoding scheme for mobile multimedia communication. In general, there are quite a large number of non-coded blocks in the encoded bitstream where all quantized DCT coefficients are truncated into zero. When the number of the non-coded blocks are known at the start of frame decoding, the amount of computation reduction can be precisely estimated for frame decoding. When the computation reduces, the operation speed and the corresponding supply voltage of VLSI circuits in the decoder also reduce, thus thus power consumption also reduces. In the proposed scheme, the number of the non-coded blocks is stored in the frame header of the encoded bitstream, and the decoder efficiently reduces the power consumption exploiting this information. Simulation results show that the proposed scheme reduces the power consumption to about 1/20.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.1-8
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• 2018

Recently, the convolutional neural network shows high performance in many computer vision tasks. However, convolutional neural networks require enormous amount of operation, so it is difficult to adopt them in the embedded environments. To solve this problem, many studies are performed on the ASIC or FPGA implementation, where an efficient representation method is required. The fixed-point representation is adequate for the ASIC or FPGA implementation but causes a performance degradation. This paper proposes a separate optimization of representations for the convolutional layers and the batch normalization layers. With the proposed method, the required bit width for the convolutional layers is reduced from 16 bits to 10 bits for the ResNet-50 neural network. Since the computation amount of the convolutional layers occupies the most of the entire computation, the bit width reduction in the convolutional layers enables the efficient implementation of the convolutional neural networks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.379-385
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• 2015

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

• Journal of the Korea Society of Computer and Information
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• v.26 no.12
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• pp.29-43
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• 2021

In this paper, a new approach to solve the constrained dynamic programming is proposed by using the constraint programming. While the conventional dynamic programming scheme has the state space augmented with states on constraints, this approach, without state augmentation, represents states of constraints as domains in a contraining programming solver. It has a hybrid computational mechanism in its computation by combining solving the Bellman equation in the dynamic programming framework and exploiting the propagation and inference methods of the constraint programming. In order to portray the differences of the two approaches, this paper solves a simple version of the long-term car rental financing problem. In the conventional scheme, data structures for state on constraints are designed, and a simple inference borrowed from the constraint programming is used to the reduction of violation of constraints because no inference risks failure of a solution. In the hybrid approach, the architecture of interface of the dynamic programming solution method and the constraint programming solution method is shown. It finally discusses the advantages of the proposed method with the conventional method.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.6
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• pp.3074-3091
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• 2019

With the widespread use of the Internet, services for providing large-capacity multimedia data such as video-on-demand (VOD) services and video uploading sites have greatly increased. VOD service providers want to be able to provide users with high-quality keyframes of high quality videos within a few minutes after the broadcast ends. However, existing keyframe extraction tends to select keyframes whose quality as a keyframe is insufficiently considered, and it takes a long computation time because it does not consider an HD class image. In this paper, we propose a keyframe selection method that flexibly applies multiple keyframe quality metrics and improves the computation time. The main procedure is as follows. After shot boundary detection is performed, the first frames are extracted as initial keyframes. The user sets evaluation metrics and priorities by considering the genre and attributes of the video. According to the evaluation metrics and the priority, the low-quality keyframe is selected as a replacement target. The replacement target keyframe is replaced with a high-quality frame in the shot. The proposed method was subjectively evaluated by 23 votes. Approximately 45% of the replaced keyframes were improved and about 18% of the replaced keyframes were adversely affected. Also, it took about 10 minutes to complete the summary of one hour video, which resulted in a reduction of more than 44.5% of the execution time.

• Journal of the Institute of Convergence Signal Processing
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• v.19 no.4
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• pp.199-205
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• 2018

So many fast motion estimation algorithms for prediction quality and computational reduction have been published due to tremendous computations of full search algorithm. In the paper, we suggest an algorithm that reduces computation effectively, while keeping prediction quality as almost same as that of the full search. The proposed algorithm based on multiple threshold filter calculates the sum of partial block matching error for each candidate, selects the candidates for the next step, compares the stability of optimal candidates with minimum error, removes impossible candidates, and calculates optimal motion vectors by determining the progress of the next step. By doing that, we can find the minimum error point as soon as possible and obtain the better performance of calculation speed by reducing unnecessary computations. The proposed algorithm can be combined with conventional fast motion estimation algorithms as well as by itself, further reduce computation while keeping the prediction quality as almost same as the algorithms, and prove it in the experimental results.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.13-26
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• 2006

RFID technology is evaluated as one of core technologies for ubiquitous environment, because of its various characteristics which barcode systems don't have. However, RFID systems have consumer's privacy infringement problems, such like information leakage and location tracing. We need RFID privacy protection protocols, that satisfy three essential security requirements; confidentiality, indistinguishability and forward security, in order to protect consumer's privacy perfectly. The most secure protocol, that satisfies all of the three essential security requirements, among existing protocols, is the hash-chain based protocol that Ohkubo proposed. Unfortunately this protocol has a big disadvantage that it takes very long time to identify a tag in the back-end server. In this paper, we propose a scheme to keep security just as it is and to reduce computation time for identifying a tag in back-end server. The proposed scheme shows the results that the identification time in back-end server is reduced considerably compared to the original scheme of Ohkubo protocol.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.3-11
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• 2011

Evaluation of cube roots in characteristic three finite fields is required for Tate (or modified Tate) pairing computation. The Hamming weights (the number of nonzero coefficients) in the polynomial representations of $x^{1/3}$ and $x^{2/3}$ determine the efficiency of cube roots computation, where $F_{3^m}$is represented as $F_3[x]/(f)$ and $f(x)=x^m+ax^k+b{\in}F_3[x]$ (a, $b{\in}F_3$) is an irreducible trinomial. O. Ahmadi et al. determined the Hamming weights of $x^{1/3}$ and $x^{2/3}$ for all irreducible trinomials. In this paper, we present formulas for cube roots in $F_{3^m}$ using the shifted polynomial basis(SPB). Moreover, we provide the suitable shifted polynomial basis bring no further modular reduction process.

• Journal of the Institute of Convergence Signal Processing
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• v.21 no.2
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• pp.55-60
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• 2020

In this paper, we propose a fast block matching algorithm of motion estimation using early detection of optimal candidate with high priority and a threshold. Even though so many fast algorithms for motion estimation have been published to reduce computational reduction full search algorithm, still so many works to improve performance of motion estimation are being reported. The proposed algorithm calculates block matching error for each candidate with high priority from previous partial matching error. The proposed algorithm can be applied additionally to most of conventional fast block matching algorithms for more speed up. By doing that, we can find the minimum error point early and get speed up by reducing unnecessary computations of impossible candidates. The proposed algorithm uses smaller computation than conventional fast full search algorithms with the same prediction quality as the full search algorithm. Experimental results shows that the proposed algorithm reduces 30~70% compared with the computation of the PDE and full search algorithms without any degradation of prediction quality and further reduces it with other fast lossy algorithms.