• 한국건축시공학회:학술대회논문집
• /
• 한국건축시공학회 2012년도 춘계 학술논문 발표대회
• /
• pp.341-343
• /
• 2012

This study introduces a method for computation of process and operation gap in the specific construction operation(i.e., RC frame construction applying a block-grouping scheme) using CYCLONE-based simulation modeling and analysis technique. Since uncertainty of construction environment exists, a thoughtful production planning is required to effectively deal with a risk resulting in schedule delay in advance. This study presents the concepts of a time delay occurred in a process level and operation level in a operation model, and a method of measuring gap-times in each level while the simulation progresses. It helps a site manager to decide how many segmentation in a construction block is suitable for eliminating unproductive time-delays under the constrained resources (e.g., laborer, equipment). A case study presents a network model representing a three segmented RC frame work, and result obtained from the simulation experiment.

• Journal of Power Electronics
• /
• 제13권4호
• /
• pp.600-608
• /
• 2013

This paper analyzes the effect of the admittance component for the digitally controlled single-phase bridgeless power factor correction (PFC) converter. To do this, it is shown how the digital delay effects such as the digital pulse-width modulation (DPWM) and the computation delays restrict the bandwidth of the converter. After that, the admittance effect of the entire digital control system is analyzed when the bridgeless PFC converter which has the limited bandwidth is connected to the grid. From this, the waveform distortion of the input current is explained and the compensation method for the admittance component is suggested to improve the quality of the input current. Both the simulations and the experiments are performed to verify the analyses taken in this paper for the 1 kW bridgeless PFC converter prototype.

• Management Science and Financial Engineering
• /
• 제5권1호
• /
• pp.1-25
• /
• 1999

There is a worldwide trend to automate the handling operations in port container terminals in an effort to improve productivity and reduce labor cost. This study iscusses how to apply an AGV(automated guided vehicle) system to the handling of containers in the yard of a port container ter-minal. The main issue of this paper is how to assign tasks of container delivery to AGVs during ship operations in an automated port container terminal. A dual-cycle operation is assumed in which the loading and the discharging operation can be performed alternately. Mixed integer linear program-ming formulations are suggested for the dispatching problem. The completion time of all the dis-charging and loading operations by a quayside crane is minimized, and the minimization of the total travel time of AGVs is also considered as a secondary objective. A heuristic method using useful properties of the dispatching problem is suggested to reduce the computational time. The perfor-mance of the heuristic algorithm is evaluated in light of solution quality and computation time.

• Journal of Communications and Networks
• /
• 제16권4호
• /
• pp.436-446
• /
• 2014

The high intensity of research and modeling in fields of mathematics, physics, biology and chemistry requires new computing resources. For the big computational complexity of such tasks computing time is large and costly. The most efficient way to increase efficiency is to adopt parallel principles. Purpose of this paper is to present the issue of parallel computing with emphasis on the analysis of parallel systems, the impact of communication delays on their efficiency and on overall execution time. Paper focuses is on finite algorithms for solving systems of linear equations, namely the matrix manipulation (Gauss elimination method, GEM). Algorithms are designed for architectures with shared memory (open multiprocessing, openMP), distributed-memory (message passing interface, MPI) and for their combination (MPI + openMP). The properties of the algorithms were analytically determined and they were experimentally verified. The conclusions are drawn for theory and practice.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
• /
• pp.346-351
• /
• 1998

In design of a digital current controller for a 3-phase (3 ) voltage-source (VS) PWM converter, its conventional model, i.e., stationary or synchronous reference frame model, is used in obtaining its discretized version. It introduces, however, inherent errors since the following practical problems are not taken into consideration: the characteristics of the space vector-based pulse-width modulation (SVPWM) and the time delays in the process of sampling and computation. In this paper, the new hybrid reference frame model of the 3 VS PWM converter is proposed considering these problems. In addition, the direct digital current controller based on this model is designed without any prediction or extrapolation algorithm to compensate the time delay. So the control algorithm is made very simple. It represents no steady-state error in input current control and has the optimized transient responses. The validity of the proposed algorithm is proved by the computer simulation and experimental results.

• 한국산업정보학회논문지
• /
• 제7권2호
• /
• pp.74-81
• /
• 2002

다중경로발생기는 일반적으로 시간지연발생부, 위상발생부, 감쇠발생부로 구성되며 주로 애널로그 방식으로 구현되어왔다. 따라서 경년변화가 발생할 수 있으며 여러 번의 A/D 변환, D/A변환과정으로 인한 신호의 충실도 저하, 미세지연을 위해 높은 주파수를 필요로 하는 단점이 있다. 본 논문은 다중경로 현상을 수학적으로 모델링하여 완전히 디지털 방식으로 구현하는 방법을 제안한다. 특히 시간지연부는 두 개의 블록으로 나누어 한 블록에서는 샘플단위의 시간지연을 만들고 나머지 한 블록에서는 섭샘플(subsample) 시간지연을 만들 수 있도록 하여 정밀한 시간지연값을 효율적으로 얻을 수 있도록 했다. 또한 시스템의 마스터 주파수도 특정한 값으로 고정할 필요도 없도록 하였다. 제안한 방법을 완전히 디지털 하드웨어로 구현해 본 논문에서 제안한 다중경로 발생 알고리듬의 타당성을 검증하였다.

• 전자공학회논문지
• /
• 제53권6호
• /
• pp.91-100
• /
• 2016

FPGA 기반 실시간 영상 워핑 시스템에서는 영상 픽셀 정보의 빠른 읽기와 메모리 접근 횟수의 감소를 위하여 영상 캐시를 활용하지만, 일반 컴퓨터 시스템의 캐시 알고리즘은 캐시 부적중(cache miss)에 의한 시간 지연과 복잡한 온라인(on-line) 연산 구조로 인하여 실시간 성능 구현에 어려움이 있다. 본 논문에서는 FPGA 기반 실시간 영상 워핑을 위한 단순한 구조의 영상 캐시 알고리즘을 제안한다. 영상 워핑에서의 픽셀 데이터 접근 순서는 워핑에 적용할 2D 좌표변환 관계에 의하여 결정되며 매 영상 프레임에서 반복되는 특성이 있다. 따라서, 캐시 로드(cache load)에 관한 사항을 오프라인(off-line)에서 미리 프로그램함으로써 캐시 부적중 상황이 발생하지 않음을 보장할 수 있고, 그 결과 온라인에서의 연산이 감소하여 캐시 컨트롤러의 구조가 단순해진다. FPGA를 활용한 전체 시스템 구조를 제시하고, 실험을 통하여 제안하는 영상 캐시 알고리즘의 정확성과 타당성을 확인한다.

• Smart Structures and Systems
• /
• 제14권6호
• /
• pp.1221-1245
• /
• 2014

Real-time hybrid simulation (RTHS) is a promising cyber-physical technique used in the experimental evaluation of civil infrastructure systems subject to dynamic loading. In RTHS, the response of a structural system is simulated by partitioning it into physical and numerical substructures, and coupling at the interface is achieved by enforcing equilibrium and compatibility in real-time. The choice of partitioning parameters will influence the overall success of the experiment. In addition, due to the dynamics of the transfer system, communication and computation delays, the feedback force signals are dependent on the system state subject to delay. Thus, the transfer system dynamics must be accommodated by appropriate actuator controllers. In light of this, guidelines should be established to facilitate successful RTHS and clearly specify: (i) the minimum requirements of the transfer system control, (ii) the minimum required sampling frequency, and (iii) the most effective ways to stabilize an unstable simulation due to the limitations of the available transfer system. The objective of this paper is to establish a stability switch criterion due to systematic experimental errors. The RTHS stability switch criterion will provide a basis for the partitioning and design of successful RTHS.

• 전기학회논문지
• /
• 제62권10호
• /
• pp.1487-1493
• /
• 2013

A new simple control method for active power filter, which can realize the complete compensation of harmonics is proposed. In the proposed scheme, a model-based digital current control strategy is presented. The proposed control system is designed and implemented in a form referred to as internal model control structure. This method provides a convenient way for parameterizing the controller in term of the nominal system model, including time-delays. As a result, the resulting controller parameters are directly set based on the power circuit parameters, which make tuning of the controllers straightforward task. In the proposed control algorithm, overshoots and oscillations due to the computation time delay is prevented by explicit incorporating of the delay in the controller transfer function. In addition, a new compensating current reference generator employing resonance model implemented by a DSP(Digital Signal Processor) is introduced. Resonance model has an infinite gain at resonant frequency, and it exhibits a band-pass filter. Consequently, the difference between the instantaneous load current and the output of this model is the current reference signal for the harmonic compensation.

• Journal of Power Electronics
• /
• 제14권6호
• /
• pp.1322-1333
• /
• 2014

To track the sinusoidal current under stationary frame and suppress the effects of low-order grid harmonics, the multi-resonant quasi-proportional plus resonant (PR) controller has been extensively used for digitally controlled LCL-type pulse-width modulation (PWM) converters with capacitor-current-feedback active damping. However, designing the controller is difficult because of its high order and large number of parameters. Moreover, the computation and PWM delays of the digitally controlled system significantly affect damping performance. In this study, the delay effect is analyzed by using the Nyquist diagrams and the system stability constraint condition can be obtained based on the Nyquist stability criterion. Moreover, impact analysis of the control parameters on the current loop performance, that is, steady-state error and stability margin, identifies that different control parameters play different decisive roles in current loop performance. Based on the analysis, a simplified controller design method based on the system specifications is proposed. Following the method, two design examples are given, and the experimental results verify the practicability and feasibility of the proposed design method.