• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.3
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• pp.275-282
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• 2013

Applications such as vibration isolation, gravity compensation, pick-and-place machines, etc., would benefit from (long-stroke) cylindrical/tubular permanent magnet (PM) actuators with integrated passive gravity compensation to minimize the power consumption. As an example, in component placing (pick-and-place) machines on printed circuit boards, passive devices allow the powerless counteraction of translator including nozzles or tooling bits. In these applications, an increasing demand is arising for high-speed actuation with high precision and bandwidth capability mainly due to the placement head being at the foundation of the motion chain, hence, a large mass of this device will result in high force/power requirements for the driving mechanism (i.e. an H-bridge with three linear permanent magnet motors placed in an H-configuration). This paper investigates a tubular actuator topology combined with passive gravity compensation. These two functionalities are separately introduced, where the combination is verified using comprehensive three dimensional (3D) finite element analyses.

• Journal of the Korea Society of Computer and Information
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• v.21 no.2
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• pp.97-103
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• 2016

This paper deals with the cycle time minimization problem that determines the productivity in printed circuit board (PCB) with n components using the m placement machines. This is known as production cycle time determination problem (PCTDP). The polynomial time algorithm to be obtain the optimal solution has been unknown yet, therefore this hard problem classified by NP-complete. This paper gets the initial assignment result with the machine has minimum unit placement time per each component firstly. Then, the balancing process with reallocation from overhead machine to underhead machine. Finally, we perform the swap optimization and get the optimal solution of cycle time $T^*$ within O(mn) computational complexity. For experimental data, the proposed algorithm can be obtain the same result as integer programming+branch-and-bound (IP+B&B) and B&B.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• KIPS Transactions on Software and Data Engineering
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• v.1 no.3
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• pp.137-148
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• 2012

Cloud service users request dedicated virtual computing resource from the cloud service provider to process jobs in independent environment from other users. To optimize this process with automated method, in this paper we proposed a framework for workflow scheduling in the cloud environment, in which the core component is the middleware called broker mediating the interaction between users and cloud service providers. To process jobs in on-demand and virtualized resources from cloud service providers, many papers propose scheduling algorithms that allocate jobs to virtual machines which are dedicated to one machine one job. With this method, the isolation of being processed jobs is guaranteed, but we can't use each resource to its fullest computing capacity with high efficiency in resource utilization. This paper therefore proposed a cost-efficient job scheduling algorithm which maximizes the utilization of managed resources with increasing the degree of multiprogramming to reduce the number of needed virtual machines; consequently we can save the cost for processing requests. We also consider the performance degradation in proposed scheme with thrashing and context switching. By evaluating the experimental results, we have shown that the proposed scheme has better cost-performance feature compared to an existing scheme.