• 제목/요약/키워드: Complexity Reduction

검색결과 672건 처리시간 0.022초

정지비행 헬리콥터 로터의 설계를 위한 공력해석 (DESIGN-ORIENTED AERODYNAMIC ANALYSES OF HELICOPTER ROTOR IN HOVER)

  • 정현주;김태승;손창호;조창열
    • 한국전산유체공학회지
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    • 제11권3호
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    • pp.1-7
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    • 2006
  • Euler and Navier-Stokes flow analyses for helicopter rotor in hover were performed as low and high fidelity analysis models respectively for the future multidisciplinary design optimization(MDO). These design-oriented analyses possess several attributes such as variable complexity, sensitivity-computation capability and modularity which analysis models involved in MDO are recommended to provide with. To realize PC-based analyses for both fidelity models, reduction of flow domain was made by appling farfield boundary condition based on 3-dimensional point sink with simple momentum theory and also periodic boundary condition in the azimuthal direction. Correlations of thrust, torque and their sensitivities between low and high complexity models were tried to evaluate the applicability of these analysis models in MDO process. It was found that the low-fidelity Euler analysis model predicted inaccurate sensitivity derivatives at relatively high angle of attack.

능동소음제어를 위한 IIR 구조 2차경로 추정 알고리즘 (IIR Structure Secondary Path Estimation Algorithms for Active Noise Control Systems)

  • 최영훈;안동준;남현도
    • 조명전기설비학회논문지
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    • 제25권2호
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    • pp.143-149
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    • 2011
  • In this paper, IIR structures are proposed to reduce the computation complexity of the secondary-pass estimation in active noise control(ANC) systems. However, there are stability problems of using IIR models to reduce the computation complexity in ANC systems. To overcome these problems, we propose a stabilizing procedure of recursive least mean squares (RLMS) algorithms for eatimating the parameters of IIR models of the secondary path transfer functions. The multichannel ANC systems are implemented by using the TMS320C6713 DSP board to test the performance of computation complexity and stability of the proposed methods. Comparing the IIR filters with the FIR filters, the IIR filters can reduce 50[%] of the computation and obtain similar noise reduction result.

Design of M-Channel IIR Uniform DFT Filter Banks Using Recursive Digital Filters

  • Dehghani, M.J.;Aravind, R.;Prabhu, K.M.M.
    • ETRI Journal
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    • 제25권5호
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    • pp.345-355
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    • 2003
  • In this paper, we propose a method for designing a class of M-channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop-band attenuation, which is also taken care of in the proposed algorithm.

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정확도 보상기를 적용한 2차원 이산 코사인 변환 프로세서의 구조 (Architecture of 2-D DCT processor adopting accuracy comensator)

  • 김견수;장순화;김재호;손경식
    • 전자공학회논문지A
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    • 제33A권10호
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    • pp.168-176
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    • 1996
  • This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

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시공간 상관성을 이용한 적응적 움직임 추정 (Adaptive motion estimation based on spatio-temporal correlations)

  • 김동욱;김진태;최종수
    • 한국통신학회논문지
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    • 제21권5호
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    • pp.1109-1122
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    • 1996
  • Generally, moving images contain the various components in motions, which reange from a static object and background to a fast moving object. To extract the accurate motion parameters, we must consider the various motions. That requires a wide search egion in motion estimation. The wide search, however, causes a high computational complexity. If we have a few knowledge about the motion direction and magnitude before motion estimation, we can determine the search location and search window size using the already-known information about the motion. In this paper, we present a local adaptive motion estimation approach that predicts a block motion based on spatio-temporal neighborhood blocks and adaptively defines the search location and search window size. This paper presents a technique for reducing computational complexity, while having high accuracy in motion estimation. The proposed algorithm is introduced the forward and backward projection techniques. The search windeo size for a block is adaptively determined by previous motion vectors and prediction errors. Simulations show significant improvements in the qualities of the motion compensated images and in the reduction of the computational complexity.

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Simplified DC Calculation Method for Simplified Depth Coding Mode of 3D High Efficiency Video Coding

  • Jo, Hyunho;Lee, Jin Young;Choi, Byeongdoo;Sim, Donggyu
    • 전자공학회논문지
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    • 제51권3호
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    • pp.139-143
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    • 2014
  • This paper proposes a simplified DC calculation method for simplified depth coding (SDC) mode of 3D High Efficiency Video Coding (3D-HEVC) to reduce the computational complexity. For the computational complexity reduction, the current reference software of 3D-HEVC employs reference samples sub-sampling method. However, accumulation, branch, and division operations are still utilized and these operations increase computational complexity. The proposed method calculates DC value without those operations. The experimental results show that the proposed method achieves 0.1% coding gain for synthesized views in common test condition (CTC) with the significantly reduced number of computing operations.

Denoising Mapping Utilizing Constellation Symmetry in Denoise-and-Forward Two-Way Relay Channels

  • Zheng, Jianping;Bai, Baoming;Li, Ying
    • ETRI Journal
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    • 제34권4호
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    • pp.617-620
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    • 2012
  • The denoising mapping with the closest-neighbor clustering (CNC) method in denoise-and-forward two-way relay channels is studied. Specifically, the symmetry of the constellations in source terminals A and B is utilized to reduce the complexity of the CNC method. The specific case considered first to illustrate how the constellation symmetry works in the CNC method is the quadrature phase-shift keying constellation in A and B and the single-antenna deployment in all terminals. This case study shows that an enormous complexity reduction can be achieved. Next, the result is extended to multiple-antenna scenarios and square quadrature amplitude modulations.

An SAD-Based Selective Bi-prediction Method for Fast Motion Estimation in High Efficiency Video Coding

  • Kim, Jongho;Jun, DongSan;Jeong, Seyoon;Cho, Sukhee;Choi, Jin Soo;Kim, Jinwoong;Ahn, Chieteuk
    • ETRI Journal
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    • 제34권5호
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    • pp.753-758
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    • 2012
  • As the next-generation video coding standard, High Efficiency Video Coding (HEVC) has adopted advanced coding tools despite the increase in computational complexity. In this paper, we propose a selective bi-prediction method to reduce the encoding complexity of HEVC. The proposed method evaluates the statistical property of the sum of absolute differences in the motion estimation process and determines whether bi-prediction is performed. A performance comparison of the complexity reduction is provided to show the effectiveness of the proposed method compared to the HEVC test model version 4.0. On average, 50% of the bi-prediction time can be reduced by the proposed method, while maintaining a negligible bit increment and a minimal loss of image quality.

H.264/AVC를 위해 inter mode에 적용된 향상된 고속 모드 결정 알고리즘 (Advanced Fast Mode Decision Algorithm Applied to Inter Mode for H.264/AVC)

  • 양상봉;조상복
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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    • pp.20-22
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    • 2007
  • The H.264/AVC standard developed by the joint Video Team (JVT) provides better coding efficiency than previous standards. The new emerging H.264/AVC employs variable block size motion estimation using multiple reference frame with 1/4-pel MV(Motion Vector) accuracy. These techniques are a important feature to accomplish higher coding efficiency. However, these techniques are increased overall computational complexity. To overcome this problem, this paper proposes advanced fast mode decision suited for variable block size by classifying inter mode based on Rate Distortion Optimization(RDO) technique. Proposed algorithm is going to use to implement H/W structure for fast mode decision. The experimental results shows that the proposed algorithm provides significant reduction computational complexity without any noticeable coding loss and additional computation. Entire computational complexity is decreased about 30%.

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재양자화 특성을 이용한 비트율 변환기의 전송률 제어 기법 (A New Rate Control algorithm for Transcoder Based-on Bit-rate Reduction Characteristics of Requantization)

  • 서광덕;이상희;권순각;유국열;김재균
    • 한국방송∙미디어공학회:학술대회논문집
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    • 한국방송공학회 1997년도 학술대회
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    • pp.181-186
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    • 1997
  • Transcoding is the key technique to further reduce the bit-rate of a previously compressed video. The performance of the transcoding is evaluated by the two factors, the accuracy on the target bit-rate and the complexity of the implementation. In this paper, were propose a new rate control algorithm which has very accurate bit-rate control performance and much smaller computational complexity. For the accuracy problem, we empirically observe the relationship between the quantization step size and generated bits in requantization process and then find that the relationship can be characterized as the new piece-wise linear model. For the complexity problem, we reduce the role of feedback rate control. The simulation results show that the proposed method gives the better performance in the accuracy with the same picture quality than conventional rat control algorithm.

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