• Title/Summary/Keyword: Compiler Testing

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Compiler에서의 Cause-Effect Graph방법을 이용한 Syntax Analysis에 관한 연구

  • 김영철;김재희
    • Proceedings of the Korean Institute of Communication Sciences Conference
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    • 1986.04a
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    • pp.189-193
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    • 1986
  • In this paper, in order to make the compiler that the corrective detection of errors and expression of more understandable error messages are provided, the usage of cause-effect testing method and case study (simulation COBOL compiler) using this methodology are illustrated.

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Test Suit Generation System for Retargetable C Compilers (재겨냥성 C 컴파일러를 위한 테스트 집합 생성 시스템)

  • Woo, Gyun;Bae, Jung-Ho;Jang, Han-Il;Lee, Yun-Jung;Chae, Heung-Seok
    • The KIPS Transactions:PartA
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    • v.16A no.4
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    • pp.245-254
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    • 2009
  • With the increasing adoption of embedded processors, the need of developing compilers for the embedded processors with timely manner is also growing. Retargeting has been adopted as a viable approach to constructing new compilers by modifying the back-end of an existing compiler. This paper proposes a test suite generation system for testing retargetable C compilers. The proposed system generates the test suite using the grammar coverage concept. Generally, the size of the test suite satisfying the grammar coverage of the source language is very large. Hence, the proposed system also provides the facility to reduce the size of the test suite. According to the experimental result, the reduced test suite can detect 75% of the compiler faults detected by the original test suite though the size of the reduced test suite is only 10% of that of the original test suite in average. This result indicates that the reduction technique proposed in this paper can be effectively used in the prior phase of the development procedure of the embedded compilers.

State-of-the-art in Quantum Computing Software (양자컴퓨팅 소프트웨어 최신 기술 동향)

  • Cho, E.Y.;Kim, Y.C.;Jung, H.B.;Cha, G.I.
    • Electronics and Telecommunications Trends
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    • v.36 no.6
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    • pp.67-77
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    • 2021
  • Since Richard Feynman presented the concept of quantum computers, quantum computing have been identified today overcoming the limits of supercomputing in various applications. Quantum hardware has steadily developed into 50 to hundreds of qubits of various quantum hardware technologies based on superconductors, semiconductors, and trapped ions over 40 years. However, it is possible to use a NISQ (Noisy Intermediate Scale Quantum) level quantum device that currently has hardware constraints. In addition, the software environment in which quantum algorithms for problem solving in various applications can be executed is pursuing research with quantum computing software such as programming language, compiler, control, testing and verification. The development of quantum software is essential amid intensifying technological competition for the commercialization of quantum computers. Therefore, this paper introduces the trends of the latest technology, focusing on quantum computing software platforms, and examines important software component technologies.

Design of A PLC Program Simulator for Nuclear Plant Using Compiler Technology (컴파일러 기술을 이용한 원전용 제어 프로그램의 시뮬레이터 설계)

  • Lee, Wan-Bok;Roh, Chang-Hyun
    • Journal of the Korea Society for Simulation
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    • v.15 no.1
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    • pp.11-17
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    • 2006
  • This paper shows a case study of designing a PLC logic simulator that was developed to simulate and verify PLC control programs for nuclear plant systems. The nuclear control system requires strict restrictions rather than normal process control system does, as it works with a high-risky and dangerous nuclear plant. One is that it should assure the safeness of the control programs by exploiting severe testing. The other restriction is that the control programs should be executed fast enough such that they could control multi devices concurrently in real-time. To cope with these restrictions, we devised a logic compiler which generates C-code programs from given PLC logic programs. Once the logic program was translated into C-code, the program could be analyzed by conventional software analysis tools and could be used to construct a fast logic simulator after cross-compiling, in fact, that is a kind of compiled-code simulator.

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Implementation and Testing of the WTP Protocol using SDL Tools (SDL 도구를 이용한 WTP 프로토콜의 구현 및 시험)

  • Lee, Hae-Dong;Jung, Ho-Won;Won, Yoo-Jae;Lim, Kyung-Shik
    • Journal of KIISE:Information Networking
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    • v.28 no.3
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    • pp.297-308
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    • 2001
  • In this paper, we design, validate and implement WTP(Wireless Transaction Protocol) using SDT(SDL Design Tool). We do modeling WTP protocol by SDL(Specification and Description Language), design and implement the environment function for the interface between the SDL system and the UDP platform and design APIs(Application Programming Interface). And we do conformance testing for WTP protocol software using ITEX(Interactive TTCN Editor and eXecutor). We write ATS(Abstract Test Suite) by TTCN(Tree and Tabular Combined Notation) and make ETS(Executable Test Suite) by the TTCN compiler supplied by ITEX.

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Reliability Evaluation of a Capacitated Two-Terminal Network (내용을 고려한 무방향 네트워크의 신뢰도 계산)

  • 최명호;윤덕균
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.12 no.20
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    • pp.47-53
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    • 1989
  • This paper presents an algorithm CAPFACT to evaluate the reliability of a capacitated two terminal network such as a communication network, a power distribution network, and a pipeline network. The network is good(working) if and only if it is possible to transmit successfully the required system capacity from one specified terminal to the other. This paper defines new Capacitated series-parallel reduction to be applied to a series-parallel structure of the network. New Capacitated factoring method is applied to a non-series-parallel structure. The method is based on the factoring theorem given by Agrawal and Barlow. According to the existing studies on the reliability evaluation of the network that the capacity is not considered, the factoring method using reduction is efficient. The CAPFACT is more efficient than Aggarwal algorithm which enumerated and combined the paths. The efficiency is proved by the result of testing the number of operations and cpu time on FORTRAN compiler of VAX-11/780 at Hanyang University.

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An Efficient Approach to Testing Retargetable Compiler Using Intermediate Representation (중간표현을 이용한 재목적 컴파일러의 효율적인 테스트 방법)

  • Jang, Han-Il;Woo, Gyun;Chae, Heung-Seok
    • Proceedings of the Korean Information Science Society Conference
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    • 2006.10b
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    • pp.575-579
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    • 2006
  • 컴파일러에 결함이 있다는 것은 곧 잘못된 코드를 생성한다는 것을 의미하므로 양질의 컴파일러 구성은 양질의 소프트웨어 생산을 위한 기본 요구조건이 된다. 임베디드 시스템이 널리 사용되면서 더욱 다양하고 복잡한 임베디드 프로세서가 개발되었고 이는 새로이 설계된 프로세서를 위한 새로운 컴파일러 개발의 필요를 야기하고 있다. 본 논문에서는 프로그램의 중간 표현을 기반으로 하는 효율적인 테스팅 방법을 제안한다. 언어의 구문 규칙을 모두 사용하는 테스트 케이스를 통해 컴파일러를 테스트하는 방법이 이미 연구되었으나, 기존의 소스 코드 수준의 방법으로는 테스트 케이스의 중복성이 존재하는 단점이 있다. 본 논문에서는 중간 표현의 구문 규칙을 이용해서 중복된 테스트 케이스를 제거하여 테스팅 효율을 증가시킬 수 있음을 기술한다. 또한 본 논문에서 제안하는 방법을 GCC의 중간 언어인 RTL에 적용한 예를 통해 설명한다.

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Automated Test Generation from Specifications Based on Formal Description Techniques

  • Chin, Byoung-Moon;Choe, Young-Han;Kim, Sung-Un;Jung, Jae-Il
    • ETRI Journal
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    • v.19 no.4
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    • pp.363-388
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    • 1997
  • This paper describes a research result on automatic generation of abstract test cases from formal specifications by applying many related algorithms and techniques such as the testing framework, rural Chinese postman tour and unique input output sequence concepts. In addition, an efficient algorithm for verifying the strong connectivity of the reference finite state machine and the concept of unique event sequence are explained. We made use of several techniques to from an integrated framework for abstract test case generation from LOTOS and SDL specifications. A prototype of the proposed framework has been built with special attention to real protocol in order to generate the executable test cases in an automatic way. The abstract test cases in tree and tabular combined notation (TTCN) language will be applied to the TTCN compiler in order to obtain the executable test cases which re relevant to the industrial application.

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A Software And Hardware Scheme For Reducing The Branch Penalty In Parallel Computers (병렬구조 컴퓨터에서 Branch penalty를 감소시키기 위한 소프트웨어와 하드웨어 방법)

  • 함찬숙;조종현;조영일
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.11
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    • pp.11-16
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    • 1993
  • VLIW architecture capable of testing multiple conditions in a cycle must support an efficient mechanism for multi-way branches. This paper proposes a mechanism to speed up the execution of multi-way branches and an efficient memory packing method of instructions, which reduced the wasted memory space. Also, we develops a new compiler technique which can transform program segments that are not applied to multi-way branches into ones that are applied to multi-way branches. The benefits gained by the transformation are to reduce branch penalty and to increase instruction-level parallelism.

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Runtime-Guard Coverage Guided Fuzzer Avoiding Deoptimization for Optimized Javascript Functions (최적화 컴파일된 자바스크립트 함수에 대한 최적화 해제 회피를 이용하는 런타임 가드 커버리지 유도 퍼저)

  • Kim, Hong-Kyo;Moon, Jong-sub
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.30 no.3
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    • pp.443-454
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    • 2020
  • The JavaScript engine is a module that receives JavaScript code as input and processes it, among many functions that are loaded into web browsers and display web pages. Many fuzzing test studies have been conducted as vulnerabilities in JavaScript engines could threaten the system security of end-users running JavaScript through browsers. Some of them have increased fuzzing efficiency by guiding test coverage in JavaScript engines, but no coverage guided fuzzing of optimized, dynamically generated machine code was attempted. Optimized JavaScript codes are difficult to perform sufficient iterative testing through fuzzing due to the function of runtime guards to free the code in the event of exceptional control flow. To solve these problems, this paper proposes a method of performing fuzzing tests on optimized machine code by avoiding deoptimization. In addition, we propose a method to measure the coverage of runtime-guards by the dynamic binary instrumentation and to guide increment of runtime-guard coverage. In our experiment, our method has outperformed the existing method at two measures: runtime coverage and iteration by time.