• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• Journal of the Korea Society for Simulation
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• v.15 no.1
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• pp.11-17
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• 2006

This paper shows a case study of designing a PLC logic simulator that was developed to simulate and verify PLC control programs for nuclear plant systems. The nuclear control system requires strict restrictions rather than normal process control system does, as it works with a high-risky and dangerous nuclear plant. One is that it should assure the safeness of the control programs by exploiting severe testing. The other restriction is that the control programs should be executed fast enough such that they could control multi devices concurrently in real-time. To cope with these restrictions, we devised a logic compiler which generates C-code programs from given PLC logic programs. Once the logic program was translated into C-code, the program could be analyzed by conventional software analysis tools and could be used to construct a fast logic simulator after cross-compiling, in fact, that is a kind of compiled-code simulator.

• Journal of Aerospace System Engineering
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• v.9 no.4
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• pp.1-7
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• 2015

The purpose of this research is to develop co-simulation methodology of codes developed in different modeling and simulation environment. We develop aerodynamic FMU(Functional Mock-up Unit) meeting FMI(Functional Mock-up Interface) specification version2 utilizing Legacy FORTRAN aerodynamic code based on unsteady vortex lattice method. It is concluded that making FMU is possible utilizing Legacy code made in any language which can be compiled and linked with object in FMI API coded in C language. This paper explains QTronic's method of using FMU SDK(Software Development Kit) and suggestion for using FORTRAN properly. Finally, we make articulated rotor/aerodynamics co-simulation by integrating aerodynamics FMU and rotor FMU developed by Modelica.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• Proceedings of the Korea Society for Simulation Conference
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• 2005.11a
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• pp.93-101
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• 2005

본 논문에서는 원전 계측제어시스템 구축을 위해 개발된 원전용 PLC 시뮬레이터의 설계 사항에 관해 소개한다. 원전용 계측제어시스템은 원전이라는 특수한 환경과 제약으로 말미암아, 일반적인 시뮬레이터 개발보다 엄격한 요건을 만족해야 한다. 이러한 요건에는 다양한 테스팅을 통하여 제어 프로그램의 안정성을 보장할 수 있어야 하며, 다수의 계측제어 프로그램들을 고속으로 동시에 실행할 수 있어야 한다. 본 논문에서는 이러한 문제점들을 극복하고자 PLC 제어 프로그램의 컴파일러를 제작하고, Compiled-Code 시뮬레이션 기법을 적용하여 고속으로 실행할 수 있는 시뮬레이터 생성 방안을 고안해 내었다.